Framework for massively parallel testing at wafer and package test

A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic...

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Hauptverfasser:	Baba, A.H., Kee Sup Kim
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit testing Hardware Logic devices Logic testing Multiprocessor interconnection networks Packaging Pins Probes System testing Very large scale integration
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container_start_page	328
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creator	Baba, A.H. Kee Sup Kim
description	A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.
doi_str_mv	10.1109/ICCD.2009.5413134
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5413134</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5413134</ieee_id><sourcerecordid>5413134</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-bf0982b0ca26d7a7895b2e761a77df8d0bc4ea9bfd9a6e0d27f19a6dcecb41b43</originalsourceid><addsrcrecordid>eNpFkMtOwzAURM1LopR-AGLjH0iwnWs7XkKgUKkSG1hX1_F1FZq0lRNR9e-JoBKzmZGOdBbD2J0UuZTCPSyq6jlXQrhcgyxkAWfsRoIC0EKVcM4mSluTGefMxT9w6pJNpDBFZkDANZv1_ZcYA3o06Al7mifs6LBLGx53iXfY9803tUe-x4RtSy0fqB-a7ZrjwA8YKXHchpHWG1zTL7xlVxHbnmannrLP-ctH9ZYt318X1eMya6TVQ-ajcKXyokZlgkVbOu0VWSPR2hDLIHwNhM7H4NCQCMpGOa5QU-1Beiim7P7P2xDRap-aDtNxdfqi-AEy7k9c</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Framework for massively parallel testing at wafer and package test</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Baba, A.H. ; Kee Sup Kim</creator><creatorcontrib>Baba, A.H. ; Kee Sup Kim</creatorcontrib><description>A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.</description><identifier>ISSN: 1063-6404</identifier><identifier>ISBN: 1424450292</identifier><identifier>ISBN: 9781424450299</identifier><identifier>EISSN: 2576-6996</identifier><identifier>EISBN: 1424450284</identifier><identifier>EISBN: 9781424450282</identifier><identifier>DOI: 10.1109/ICCD.2009.5413134</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit testing ; Hardware ; Logic devices ; Logic testing ; Multiprocessor interconnection networks ; Packaging ; Pins ; Probes ; System testing ; Very large scale integration</subject><ispartof>2009 IEEE International Conference on Computer Design, 2009, p.328-334</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5413134$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5413134$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Baba, A.H.</creatorcontrib><creatorcontrib>Kee Sup Kim</creatorcontrib><title>Framework for massively parallel testing at wafer and package test</title><title>2009 IEEE International Conference on Computer Design</title><addtitle>ICCD</addtitle><description>A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.</description><subject>Circuit testing</subject><subject>Hardware</subject><subject>Logic devices</subject><subject>Logic testing</subject><subject>Multiprocessor interconnection networks</subject><subject>Packaging</subject><subject>Pins</subject><subject>Probes</subject><subject>System testing</subject><subject>Very large scale integration</subject><issn>1063-6404</issn><issn>2576-6996</issn><isbn>1424450292</isbn><isbn>9781424450299</isbn><isbn>1424450284</isbn><isbn>9781424450282</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkMtOwzAURM1LopR-AGLjH0iwnWs7XkKgUKkSG1hX1_F1FZq0lRNR9e-JoBKzmZGOdBbD2J0UuZTCPSyq6jlXQrhcgyxkAWfsRoIC0EKVcM4mSluTGefMxT9w6pJNpDBFZkDANZv1_ZcYA3o06Al7mifs6LBLGx53iXfY9803tUe-x4RtSy0fqB-a7ZrjwA8YKXHchpHWG1zTL7xlVxHbnmannrLP-ctH9ZYt318X1eMya6TVQ-ajcKXyokZlgkVbOu0VWSPR2hDLIHwNhM7H4NCQCMpGOa5QU-1Beiim7P7P2xDRap-aDtNxdfqi-AEy7k9c</recordid><startdate>200910</startdate><enddate>200910</enddate><creator>Baba, A.H.</creator><creator>Kee Sup Kim</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200910</creationdate><title>Framework for massively parallel testing at wafer and package test</title><author>Baba, A.H. ; Kee Sup Kim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-bf0982b0ca26d7a7895b2e761a77df8d0bc4ea9bfd9a6e0d27f19a6dcecb41b43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Circuit testing</topic><topic>Hardware</topic><topic>Logic devices</topic><topic>Logic testing</topic><topic>Multiprocessor interconnection networks</topic><topic>Packaging</topic><topic>Pins</topic><topic>Probes</topic><topic>System testing</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Baba, A.H.</creatorcontrib><creatorcontrib>Kee Sup Kim</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Baba, A.H.</au><au>Kee Sup Kim</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Framework for massively parallel testing at wafer and package test</atitle><btitle>2009 IEEE International Conference on Computer Design</btitle><stitle>ICCD</stitle><date>2009-10</date><risdate>2009</risdate><spage>328</spage><epage>334</epage><pages>328-334</pages><issn>1063-6404</issn><eissn>2576-6996</eissn><isbn>1424450292</isbn><isbn>9781424450299</isbn><eisbn>1424450284</eisbn><eisbn>9781424450282</eisbn><abstract>A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.</abstract><pub>IEEE</pub><doi>10.1109/ICCD.2009.5413134</doi><tpages>7</tpages><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier	ISSN: 1063-6404
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issn	1063-6404 2576-6996
language	eng
recordid	cdi_ieee_primary_5413134
source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Circuit testing Hardware Logic devices Logic testing Multiprocessor interconnection networks Packaging Pins Probes System testing Very large scale integration
title	Framework for massively parallel testing at wafer and package test
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-19T10%3A56%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Framework%20for%20massively%20parallel%20testing%20at%20wafer%20and%20package%20test&rft.btitle=2009%20IEEE%20International%20Conference%20on%20Computer%20Design&rft.au=Baba,%20A.H.&rft.date=2009-10&rft.spage=328&rft.epage=334&rft.pages=328-334&rft.issn=1063-6404&rft.eissn=2576-6996&rft.isbn=1424450292&rft.isbn_list=9781424450299&rft_id=info:doi/10.1109/ICCD.2009.5413134&rft_dat=%3Cieee_6IE%3E5413134%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424450284&rft.eisbn_list=9781424450282&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5413134&rfr_iscdi=true