FPGA-based implementation of a CFAR processor using Batcher's sort and LUT arithmetic
This paper presents the realization of the forward automatic censored cell averaging detector (F-ACCAD), a novel CFAR algorithm for detecting targets in log-normal distribution clutter recently published . The algorithm is realized through an FPGA-based parallel architecture. The timing constraints...
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| creator | Seddiq, Y.M. Alshebeili, S.A. Alhumaidi, S.M. Obied, A.M. |
| description | This paper presents the realization of the forward automatic censored cell averaging detector (F-ACCAD), a novel CFAR algorithm for detecting targets in log-normal distribution clutter recently published . The algorithm is realized through an FPGA-based parallel architecture. The timing constraints of high resolution radar applications are considered and satisfied in the system. The sequential nature of the algorithm has been parallelized to achieve the desired processing delay. The intensive statistical calculations and the complexity of the algorithm have been significantly reduced by using lookup tables (LUTs). Batcher's sort, a parallel sorting algorithm, is adopted in this work. The hardware synthesis results and timing analysis are reported at the end. |
| doi_str_mv | 10.1109/IDT.2009.5404087 |
| format | Conference Proceeding |
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The hardware synthesis results and timing analysis are reported at the end.</description><subject>Arithmetic</subject><subject>Batcher's sort</subject><subject>CFAR</subject><subject>Clutter</subject><subject>Delay</subject><subject>Detectors</subject><subject>FPGA</subject><subject>hardware implmantation</subject><subject>Log-normal distribution</subject><subject>LUT arithmetic</subject><subject>Parallel architectures</subject><subject>Radar</subject><subject>Radar applications</subject><subject>Radar detection</subject><subject>Table lookup</subject><subject>Timing</subject><issn>2162-0601</issn><isbn>9781424457489</isbn><isbn>1424457483</isbn><isbn>1424457505</isbn><isbn>9781424457502</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotUMFKw0AUXFHBWnsXvOzNU-rbzW6SPdZoayGgSHouL5u3dqVJSnY9-PcG7FyGGYZhGMbuBSyFAPO0famXEsAstQIFRX7BboWSSulcg75kC5MXZ60Kc8VmUmQygQzEDVuE8A0TlJZGmBnbrT82q6TBQC333elIHfURox96PjiOvFyvPvlpHCyFMIz8J_j-iz9jtAcaHwOfvMixb3m1qzmOPh46it7esWuHx0CLM89ZvX6ty7eket9sy1WVeAMxkbKVWlgHGsw0N1ONcy1ZDahEkaeS0BYWMpEjNk1TSNvoKSTAaUrRIaVz9vBf64lofxp9h-Pv_nxK-gfVaFJ0</recordid><startdate>200911</startdate><enddate>200911</enddate><creator>Seddiq, Y.M.</creator><creator>Alshebeili, S.A.</creator><creator>Alhumaidi, S.M.</creator><creator>Obied, A.M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200911</creationdate><title>FPGA-based implementation of a CFAR processor using Batcher's sort and LUT arithmetic</title><author>Seddiq, Y.M. ; Alshebeili, S.A. ; Alhumaidi, S.M. ; Obied, A.M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-22d251cf050942464bffdec50a418732eac8c0617aabbb82cb546410f5e3afae3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Arithmetic</topic><topic>Batcher's sort</topic><topic>CFAR</topic><topic>Clutter</topic><topic>Delay</topic><topic>Detectors</topic><topic>FPGA</topic><topic>hardware implmantation</topic><topic>Log-normal distribution</topic><topic>LUT arithmetic</topic><topic>Parallel architectures</topic><topic>Radar</topic><topic>Radar applications</topic><topic>Radar detection</topic><topic>Table lookup</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Seddiq, Y.M.</creatorcontrib><creatorcontrib>Alshebeili, S.A.</creatorcontrib><creatorcontrib>Alhumaidi, S.M.</creatorcontrib><creatorcontrib>Obied, A.M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Seddiq, Y.M.</au><au>Alshebeili, S.A.</au><au>Alhumaidi, S.M.</au><au>Obied, A.M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>FPGA-based implementation of a CFAR processor using Batcher's sort and LUT arithmetic</atitle><btitle>2009 4th International Design and Test Workshop (IDT)</btitle><stitle>IDT</stitle><date>2009-11</date><risdate>2009</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><issn>2162-0601</issn><isbn>9781424457489</isbn><isbn>1424457483</isbn><eisbn>1424457505</eisbn><eisbn>9781424457502</eisbn><abstract>This paper presents the realization of the forward automatic censored cell averaging detector (F-ACCAD), a novel CFAR algorithm for detecting targets in log-normal distribution clutter recently published . The algorithm is realized through an FPGA-based parallel architecture. The timing constraints of high resolution radar applications are considered and satisfied in the system. The sequential nature of the algorithm has been parallelized to achieve the desired processing delay. The intensive statistical calculations and the complexity of the algorithm have been significantly reduced by using lookup tables (LUTs). Batcher's sort, a parallel sorting algorithm, is adopted in this work. The hardware synthesis results and timing analysis are reported at the end.</abstract><pub>IEEE</pub><doi>10.1109/IDT.2009.5404087</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 2162-0601 |
| ispartof | 2009 4th International Design and Test Workshop (IDT), 2009, p.1-6 |
| issn | 2162-0601 |
| language | eng |
| recordid | cdi_ieee_primary_5404087 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Arithmetic Batcher's sort CFAR Clutter Delay Detectors FPGA hardware implmantation Log-normal distribution LUT arithmetic Parallel architectures Radar Radar applications Radar detection Table lookup Timing |
| title | FPGA-based implementation of a CFAR processor using Batcher's sort and LUT arithmetic |
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