A re-use methodology for formal SoC protocol compliance verification

We propose a new methodology for formally specifying on-chip bus protocols and for verifying protocol compliance of communication blocks in System-on-Chip (SoC) designs. In this methodology, the bus protocol is specified in a design-independent way by a set of protocol compliance properties based on...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Nguyen, M.D., Thalmaier, M., Wedler, M., Stoffel, D., Kunz, W., Bormann, J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits Error correction Intellectual property Monitoring Productivity Protocols Reachability analysis Signal design System-on-a-chip Watches
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