High performance, low latency double digit decimal multiplier on ASIC and FPGA
Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clo...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1450 |
|---|---|
| container_issue | |
| container_start_page | 1445 |
| container_title | |
| container_volume | |
| creator | James, R.K. Jacob, K.P. Sasi, S. |
| description | Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard. |
| doi_str_mv | 10.1109/NABIC.2009.5393703 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5393703</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5393703</ieee_id><sourcerecordid>5393703</sourcerecordid><originalsourceid>FETCH-LOGICAL-i1343-7cab6bf7976473d311098ac6da3aebec5c10fa55f1180e9381b59ae970969cd83</originalsourceid><addsrcrecordid>eNotj11LwzAYhQMy0M39Ab3JD7A16Zs0zWUtbiuMKajXI03ezkj6Qdsh-_duuHNzLg48nIeQB85izpl-3uUvZREnjOlYggbF4IbMuUiEkEyCnJH5ZdNMcZC3ZDmOP-wcIRNg8o7sNv7wTXsc6m5oTGvxiYbulwYzYWtP1HXHKiB1_uAn6tD6xgTaHMPk--BxoF1L84-yoKZ1dPW-zu_JrDZhxOW1F-Rr9fpZbKLt27os8m3kOQiIlDVVWtVKq1QocHARyYxNnQGDFVppOauNlDXnGUMNGa-kNqgV06m2LoMFefznekTc98P513DaX_3hD1wxTZ0</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>High performance, low latency double digit decimal multiplier on ASIC and FPGA</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>James, R.K. ; Jacob, K.P. ; Sasi, S.</creator><creatorcontrib>James, R.K. ; Jacob, K.P. ; Sasi, S.</creatorcontrib><description>Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.</description><identifier>ISBN: 1424450535</identifier><identifier>ISBN: 9781424450534</identifier><identifier>DOI: 10.1109/NABIC.2009.5393703</identifier><identifier>LCCN: 2009907135</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application specific integrated circuits ; ASIC ; Carry Save Adders ; Clocks ; Computational modeling ; Decimal Multipliers ; Delay ; Field programmable gate arrays ; FPGA ; Graphics ; High Performance ; Internet ; Libraries ; Logic ; Throughput</subject><ispartof>2009 World Congress on Nature & Biologically Inspired Computing (NaBIC), 2009, p.1445-1450</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5393703$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5393703$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>James, R.K.</creatorcontrib><creatorcontrib>Jacob, K.P.</creatorcontrib><creatorcontrib>Sasi, S.</creatorcontrib><title>High performance, low latency double digit decimal multiplier on ASIC and FPGA</title><title>2009 World Congress on Nature & Biologically Inspired Computing (NaBIC)</title><addtitle>NABIC</addtitle><description>Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.</description><subject>Application specific integrated circuits</subject><subject>ASIC</subject><subject>Carry Save Adders</subject><subject>Clocks</subject><subject>Computational modeling</subject><subject>Decimal Multipliers</subject><subject>Delay</subject><subject>Field programmable gate arrays</subject><subject>FPGA</subject><subject>Graphics</subject><subject>High Performance</subject><subject>Internet</subject><subject>Libraries</subject><subject>Logic</subject><subject>Throughput</subject><isbn>1424450535</isbn><isbn>9781424450534</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj11LwzAYhQMy0M39Ab3JD7A16Zs0zWUtbiuMKajXI03ezkj6Qdsh-_duuHNzLg48nIeQB85izpl-3uUvZREnjOlYggbF4IbMuUiEkEyCnJH5ZdNMcZC3ZDmOP-wcIRNg8o7sNv7wTXsc6m5oTGvxiYbulwYzYWtP1HXHKiB1_uAn6tD6xgTaHMPk--BxoF1L84-yoKZ1dPW-zu_JrDZhxOW1F-Rr9fpZbKLt27os8m3kOQiIlDVVWtVKq1QocHARyYxNnQGDFVppOauNlDXnGUMNGa-kNqgV06m2LoMFefznekTc98P513DaX_3hD1wxTZ0</recordid><startdate>200912</startdate><enddate>200912</enddate><creator>James, R.K.</creator><creator>Jacob, K.P.</creator><creator>Sasi, S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200912</creationdate><title>High performance, low latency double digit decimal multiplier on ASIC and FPGA</title><author>James, R.K. ; Jacob, K.P. ; Sasi, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i1343-7cab6bf7976473d311098ac6da3aebec5c10fa55f1180e9381b59ae970969cd83</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Application specific integrated circuits</topic><topic>ASIC</topic><topic>Carry Save Adders</topic><topic>Clocks</topic><topic>Computational modeling</topic><topic>Decimal Multipliers</topic><topic>Delay</topic><topic>Field programmable gate arrays</topic><topic>FPGA</topic><topic>Graphics</topic><topic>High Performance</topic><topic>Internet</topic><topic>Libraries</topic><topic>Logic</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>James, R.K.</creatorcontrib><creatorcontrib>Jacob, K.P.</creatorcontrib><creatorcontrib>Sasi, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>James, R.K.</au><au>Jacob, K.P.</au><au>Sasi, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High performance, low latency double digit decimal multiplier on ASIC and FPGA</atitle><btitle>2009 World Congress on Nature & Biologically Inspired Computing (NaBIC)</btitle><stitle>NABIC</stitle><date>2009-12</date><risdate>2009</risdate><spage>1445</spage><epage>1450</epage><pages>1445-1450</pages><isbn>1424450535</isbn><isbn>9781424450534</isbn><abstract>Decimal multiplication is an integral part of financial, commercial, and internet-based computations. This paper presents a novel double digit decimal multiplication (DDDM) technique that offers low latency and high throughput. This design performs two digit multiplications simultaneously in one clock cycle. Double digit fixed point decimal multipliers for 7digit, 16 digit and 34 digit are simulated using Leonardo Spectrum from Mentor Graphics Corporation using ASIC Library. The paper also presents area and delay comparisons for these fixed point multipliers on Xilinx, Altera, Actel and Quick logic FPGAs. This multiplier design can be extended to support decimal floating point multiplication for IEEE 754- 2008 standard.</abstract><pub>IEEE</pub><doi>10.1109/NABIC.2009.5393703</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 1424450535 |
| ispartof | 2009 World Congress on Nature & Biologically Inspired Computing (NaBIC), 2009, p.1445-1450 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_5393703 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application specific integrated circuits ASIC Carry Save Adders Clocks Computational modeling Decimal Multipliers Delay Field programmable gate arrays FPGA Graphics High Performance Internet Libraries Logic Throughput |
| title | High performance, low latency double digit decimal multiplier on ASIC and FPGA |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T20%3A43%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=High%20performance,%20low%20latency%20double%20digit%20decimal%20multiplier%20on%20ASIC%20and%20FPGA&rft.btitle=2009%20World%20Congress%20on%20Nature%20&%20Biologically%20Inspired%20Computing%20(NaBIC)&rft.au=James,%20R.K.&rft.date=2009-12&rft.spage=1445&rft.epage=1450&rft.pages=1445-1450&rft.isbn=1424450535&rft.isbn_list=9781424450534&rft_id=info:doi/10.1109/NABIC.2009.5393703&rft_dat=%3Cieee_6IE%3E5393703%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5393703&rfr_iscdi=true |