Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing
In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in wave dynamic differential logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algor...
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| creator | Amouri, E. Mrabet, H. Marrakchi, Z. Mehrez, H. |
| description | In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in wave dynamic differential logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results demonstrate that our placement and routing techniques reduce the delay unbalance significantly. They achieve 93% of average timing balancing improvement in WDDL designs. |
| doi_str_mv | 10.1109/ReConFig.2009.44 |
| format | Conference Proceeding |
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| ispartof | 2009 International Conference on Reconfigurable Computing and FPGAs, 2009, p.201-206 |
| issn | 2325-6532 2640-0472 |
| language | eng |
| recordid | cdi_ieee_primary_5382052 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Computer Science Cryptography Delay Differential Power Analysis Energy consumption Field programmable gate arrays Logic MFPGA Page description languages Placement Rails Routing Security Timing Timing balance WDDL |
| title | Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing |
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