High speed merged-datapath design for run-time reconfigurable systems

Datapath merging is an efficient high level synthesis method to merge data flow graphs (DFGs), corresponding to two or more computational intensive loops. This process creates a general purpose datapaths (merged datapaths) instead of multiple datapaths that results in shorter bit-stream length and therefore reduces the configuration time in reconfigurable systems. The merged datapath, however has worse loop execution time. This paper represents two datapath merging algorithms to address this problem. These algorithms consider the impact of adding multiplexer's latency to the critical path delay of the merged datapath. The former algorithm merges DFGs from the biggest DFG to the smallest one to make high speed merged datapath. The latter merges DFGs in steps, and in the final step, it combines the resources inside the merged datapath to achieve additional reduction in configuration time. The proposed techniques are evaluated using several Mediabench applications. The experimental results show a significant reduction, up to 35% in loops execution time for the first algorithm and up to 27% reduction for the second algorithm in comparison to previous datapath merging algorithm.