Pretreatment in Automatic Checking of Schematic Design
For the differences among schematics which have been designed with different electronic design automatic (EDA) tools, a kind of interface file system based on certain checking rules is proposed and designed in this paper. Checking designed data of schematics automatically and heterogeneously will co...
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| creator | Jianguo Jiang Kang Shi Lidi Jiang Gaili Duan |
| description | For the differences among schematics which have been designed with different electronic design automatic (EDA) tools, a kind of interface file system based on certain checking rules is proposed and designed in this paper. Checking designed data of schematics automatically and heterogeneously will come true by converting different schematics to the interface file. The conversion process is called pretreatment. In addition, this paper analyzes schematic files which have been designed with three kinds of different EDA tools, and will show the process of the pretreatment of Protel schematic file as an example. |
| doi_str_mv | 10.1109/ICIECS.2009.5362715 |
| format | Conference Proceeding |
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Checking designed data of schematics automatically and heterogeneously will come true by converting different schematics to the interface file. The conversion process is called pretreatment. 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Checking designed data of schematics automatically and heterogeneously will come true by converting different schematics to the interface file. The conversion process is called pretreatment. In addition, this paper analyzes schematic files which have been designed with three kinds of different EDA tools, and will show the process of the pretreatment of Protel schematic file as an example.</description><subject>Circuits</subject><subject>Computer interfaces</subject><subject>Cultural differences</subject><subject>Data analysis</subject><subject>Data mining</subject><subject>Education</subject><subject>Electronic design automation and methodology</subject><subject>File systems</subject><subject>Military computing</subject><subject>Pins</subject><issn>2156-7379</issn><issn>2156-7387</issn><isbn>9781424449941</isbn><isbn>1424449944</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kN1Kw0AUhBe1YK15gt7kBRJ3z_6c7GWJtQYKCu192U3PtqsmlWS98O1VWrwamOEbhmFsLngpBLcPTd0s600JnNtSSwMo9BWbgtCmQFnhNcssVkKBUspaJW7-M7QTdveHWW4MVrcsG8c3zrmAyoCFKTOvA6WBXOqoT3ns88VXOnUuxTavj9S-x_6Qn0K-aY90dh9pjIf-nk2C-xgpu-iMbZ-W2_q5WL-smnqxLqLlqcDgLe4rKdCB-h1IjrB1ygUtrW8dGQhckUKE4LQQEjxYA87jXnvtg5AzNj_XRiLafQ6xc8P37vKA_AHcekrV</recordid><startdate>200912</startdate><enddate>200912</enddate><creator>Jianguo Jiang</creator><creator>Kang Shi</creator><creator>Lidi Jiang</creator><creator>Gaili Duan</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200912</creationdate><title>Pretreatment in Automatic Checking of Schematic Design</title><author>Jianguo Jiang ; Kang Shi ; Lidi Jiang ; Gaili Duan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-7fb97d8317a24781eae7ca4af539bcae62f04e4772fa51132b2962ab7d5b5bf13</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Circuits</topic><topic>Computer interfaces</topic><topic>Cultural differences</topic><topic>Data analysis</topic><topic>Data mining</topic><topic>Education</topic><topic>Electronic design automation and methodology</topic><topic>File systems</topic><topic>Military computing</topic><topic>Pins</topic><toplevel>online_resources</toplevel><creatorcontrib>Jianguo Jiang</creatorcontrib><creatorcontrib>Kang Shi</creatorcontrib><creatorcontrib>Lidi Jiang</creatorcontrib><creatorcontrib>Gaili Duan</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jianguo Jiang</au><au>Kang Shi</au><au>Lidi Jiang</au><au>Gaili Duan</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Pretreatment in Automatic Checking of Schematic Design</atitle><btitle>2009 International Conference on Information Engineering and Computer Science</btitle><stitle>ICIECS</stitle><date>2009-12</date><risdate>2009</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>2156-7379</issn><eissn>2156-7387</eissn><isbn>9781424449941</isbn><isbn>1424449944</isbn><abstract>For the differences among schematics which have been designed with different electronic design automatic (EDA) tools, a kind of interface file system based on certain checking rules is proposed and designed in this paper. Checking designed data of schematics automatically and heterogeneously will come true by converting different schematics to the interface file. The conversion process is called pretreatment. In addition, this paper analyzes schematic files which have been designed with three kinds of different EDA tools, and will show the process of the pretreatment of Protel schematic file as an example.</abstract><pub>IEEE</pub><doi>10.1109/ICIECS.2009.5362715</doi><tpages>4</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Computer interfaces Cultural differences Data analysis Data mining Education Electronic design automation and methodology File systems Military computing Pins |
| title | Pretreatment in Automatic Checking of Schematic Design |
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