Transaction Level Modeling and Design Space Exploration for SOC Test Architectures

Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the p...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Chin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Su, A.P.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bandwidth Delay Design methodology Electronic system level (ESL) Integrated circuit testing Performance evaluation Signal design SOC testing Space exploration System testing System-level design test architecture test platform Throughput transaction level modeling (TLM)
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