A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency
An advance in folding-interpolating analog-to-digital converters (ADCs) is demonstrated which simplifies their extension to higher resolution by building the converter out of identical but scaled pipelined cascaded folding stages. In this unified folding architecture the parallel coarse channel has...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2009-12, Vol.44 (12), p.3294-3304 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 44 |
| creator | Taft, Robert C. Francese, Pier Andrea Tursi, Maria Rosaria Hidri, Ols MacKenzie, Alan Hohn, Tobias Schmitz, Philipp Werker, Heinz Glenny, Andrew |
| description | An advance in folding-interpolating analog-to-digital converters (ADCs) is demonstrated which simplifies their extension to higher resolution by building the converter out of identical but scaled pipelined cascaded folding stages. In this unified folding architecture the parallel coarse channel has been eliminated by recursively using the previous folding stage as the coarse channel for each following cascaded stage. This new architecture is demonstrated in a 10-bit ADC using six cascaded folding-by-3 stages with a total folding order of 729. At 1.0 GS/s, this interleave-by-2 ADC achieves |
| doi_str_mv | 10.1109/JSSC.2009.2032634 |
| format | Article |
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In this unified folding architecture the parallel coarse channel has been eliminated by recursively using the previous folding stage as the coarse channel for each following cascaded stage. This new architecture is demonstrated in a 10-bit ADC using six cascaded folding-by-3 stages with a total folding order of 729. At 1.0 GS/s, this interleave-by-2 ADC achieves <±0.2 LSB DNL, ¿ ±0.5 LSB INL, 9.2 ENOB at 100 MHz input, 9.1 ENOB at Nyquist, and 8.8 ENOB at 1 GHz input. The value at F IN = 1 GHz is 1 ENOB higher than any value published to date. The power consumption from a single 1.8 V supply is 1.2 W/channel which includes the LVDS drivers for this dual-channel (I and Q each running at 1 GS/s) ADC.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2009.2032634</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Analog-digital conversion ; Analog-to-digital conversion ; Architecture ; Buildings ; Calibration ; Channels ; Circuits ; CMOS analog integrated circuits ; CMOS technology ; Converters ; Driver circuits ; Drivers ; Energy consumption ; Folding ; Frequency conversion ; high-speed techniques ; interpolation ; Nyquist converter ; Nyquist frequencies ; pipelined ; Running ; Signal resolution ; Voltage</subject><ispartof>IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3294-3304</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c355t-5ce176c81f6307badad74262ca54e610d05b0dd0d055f16cfc41b126766bf2523</citedby><cites>FETCH-LOGICAL-c355t-5ce176c81f6307badad74262ca54e610d05b0dd0d055f16cfc41b126766bf2523</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5342348$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,782,786,798,27933,27934,54767</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5342348$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Taft, Robert C.</creatorcontrib><creatorcontrib>Francese, Pier Andrea</creatorcontrib><creatorcontrib>Tursi, Maria Rosaria</creatorcontrib><creatorcontrib>Hidri, Ols</creatorcontrib><creatorcontrib>MacKenzie, Alan</creatorcontrib><creatorcontrib>Hohn, Tobias</creatorcontrib><creatorcontrib>Schmitz, Philipp</creatorcontrib><creatorcontrib>Werker, Heinz</creatorcontrib><creatorcontrib>Glenny, Andrew</creatorcontrib><title>A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>An advance in folding-interpolating analog-to-digital converters (ADCs) is demonstrated which simplifies their extension to higher resolution by building the converter out of identical but scaled pipelined cascaded folding stages. In this unified folding architecture the parallel coarse channel has been eliminated by recursively using the previous folding stage as the coarse channel for each following cascaded stage. This new architecture is demonstrated in a 10-bit ADC using six cascaded folding-by-3 stages with a total folding order of 729. At 1.0 GS/s, this interleave-by-2 ADC achieves <±0.2 LSB DNL, ¿ ±0.5 LSB INL, 9.2 ENOB at 100 MHz input, 9.1 ENOB at Nyquist, and 8.8 ENOB at 1 GHz input. The value at F IN = 1 GHz is 1 ENOB higher than any value published to date. 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| subjects | Analog-digital conversion Analog-to-digital conversion Architecture Buildings Calibration Channels Circuits CMOS analog integrated circuits CMOS technology Converters Driver circuits Drivers Energy consumption Folding Frequency conversion high-speed techniques interpolation Nyquist converter Nyquist frequencies pipelined Running Signal resolution Voltage |
| title | A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency |
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