Analysis of Single-Event Transients in Integer- N Frequency Dividers and Hardness Assurance Implications for Phase-Locked Loops
Single-event transients (SET) are analyzed in integer- N frequency dividers configured internal and external to a closed-loop phase-locked loop (PLL) circuit. Simulations, corroborated by experimental results, indicate that the location and gain of the frequency divider in any PLL arrangement strong...
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| Veröffentlicht in: | IEEE transactions on nuclear science 2009-12, Vol.56 (6), p.3489-3498 |
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| container_title | IEEE transactions on nuclear science |
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| creator | Loveless, T.D. Olson, B.D. Bhuva, B.L. Holman, W.T. Hafer, C.C. Massengill, L.W. |
| description | Single-event transients (SET) are analyzed in integer- N frequency dividers configured internal and external to a closed-loop phase-locked loop (PLL) circuit. Simulations, corroborated by experimental results, indicate that the location and gain of the frequency divider in any PLL arrangement strongly influence both the error rate of the PLL circuit and the propagation of transients through the closed-loop. The probability of an ion-strike causing output phase displacement values on the order of the operating-period can be significantly reduced by increasing the divisor of the stand-alone output frequency divider. Conversely, increasing the feedback divisor is shown to magnify SETs propagating through the closed-loop PLL. |
| doi_str_mv | 10.1109/TNS.2009.2033918 |
| format | Article |
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Simulations, corroborated by experimental results, indicate that the location and gain of the frequency divider in any PLL arrangement strongly influence both the error rate of the PLL circuit and the propagation of transients through the closed-loop. The probability of an ion-strike causing output phase displacement values on the order of the operating-period can be significantly reduced by increasing the divisor of the stand-alone output frequency divider. Conversely, increasing the feedback divisor is shown to magnify SETs propagating through the closed-loop PLL.</description><subject>Assurance</subject><subject>Circuit simulation</subject><subject>Circuit topology</subject><subject>Circuits</subject><subject>CMOS technology</subject><subject>Displacement</subject><subject>Error analysis</subject><subject>Frequency conversion</subject><subject>Frequency dividers</subject><subject>Frequency synthesizers</subject><subject>Gain</subject><subject>Hardness</subject><subject>Image analysis</subject><subject>Integrated circuit synthesis</subject><subject>Phase locked loops</subject><subject>Propagation</subject><subject>radiation effects</subject><subject>Simulation</subject><subject>single event effects</subject><subject>single event transients</subject><subject>Transient analysis</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1rGzEQxUVoIa7be6AX3XpaR1ppd6WjcZPGYJxA3PMiSyNH7VpyNeuAT_nXK-OQy3zAe_OGHyE3nM04Z_p2s36e1YzpUoTQXF2RCW8aVfGmU5_IhDGuKi21viZfEP-UVTasmZC3eTTDCQPS5OlziLsBqrtXiCPdZBMxlAlpiHQZR9hBruia3mf4d4RoT_RneA0OMlITHX0w2UVApHPEY_FaoMv9YQjWjCFFpD5l-vRiEKpVsn_B0VVKB_xKPnszIHx771Py-_5us3ioVo-_lov5qrK1bsaqE1JZZXTXqXbLammh7hTTHYOtV_VWgne2Ndva1160TgOAMU56YR24TjojpuTH5e4hp_I9jv0-oIVhMBHSEXvVatWoVqqiZBelzQkxg-8POexNPvWc9WfUfUHdn1H376iL5fvFEkrwh7wRkotWif8sgX0i</recordid><startdate>20091201</startdate><enddate>20091201</enddate><creator>Loveless, T.D.</creator><creator>Olson, B.D.</creator><creator>Bhuva, B.L.</creator><creator>Holman, W.T.</creator><creator>Hafer, C.C.</creator><creator>Massengill, L.W.</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope></search><sort><creationdate>20091201</creationdate><title>Analysis of Single-Event Transients in Integer- N Frequency Dividers and Hardness Assurance Implications for Phase-Locked Loops</title><author>Loveless, T.D. ; Olson, B.D. ; Bhuva, B.L. ; Holman, W.T. ; Hafer, C.C. ; Massengill, L.W.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c295t-7348c8a97786b024ce2780970ebf82b4efdc6ab2f2f36d9eeeaad4f3cded74da3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Assurance</topic><topic>Circuit simulation</topic><topic>Circuit topology</topic><topic>Circuits</topic><topic>CMOS technology</topic><topic>Displacement</topic><topic>Error analysis</topic><topic>Frequency conversion</topic><topic>Frequency dividers</topic><topic>Frequency synthesizers</topic><topic>Gain</topic><topic>Hardness</topic><topic>Image analysis</topic><topic>Integrated circuit synthesis</topic><topic>Phase locked loops</topic><topic>Propagation</topic><topic>radiation effects</topic><topic>Simulation</topic><topic>single event effects</topic><topic>single event transients</topic><topic>Transient analysis</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Loveless, T.D.</creatorcontrib><creatorcontrib>Olson, B.D.</creatorcontrib><creatorcontrib>Bhuva, B.L.</creatorcontrib><creatorcontrib>Holman, W.T.</creatorcontrib><creatorcontrib>Hafer, C.C.</creatorcontrib><creatorcontrib>Massengill, L.W.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on nuclear science</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Loveless, T.D.</au><au>Olson, B.D.</au><au>Bhuva, B.L.</au><au>Holman, W.T.</au><au>Hafer, C.C.</au><au>Massengill, L.W.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analysis of Single-Event Transients in Integer- N Frequency Dividers and Hardness Assurance Implications for Phase-Locked Loops</atitle><jtitle>IEEE transactions on nuclear science</jtitle><stitle>TNS</stitle><date>2009-12-01</date><risdate>2009</risdate><volume>56</volume><issue>6</issue><spage>3489</spage><epage>3498</epage><pages>3489-3498</pages><issn>0018-9499</issn><eissn>1558-1578</eissn><coden>IETNAE</coden><abstract>Single-event transients (SET) are analyzed in integer- N frequency dividers configured internal and external to a closed-loop phase-locked loop (PLL) circuit. Simulations, corroborated by experimental results, indicate that the location and gain of the frequency divider in any PLL arrangement strongly influence both the error rate of the PLL circuit and the propagation of transients through the closed-loop. The probability of an ion-strike causing output phase displacement values on the order of the operating-period can be significantly reduced by increasing the divisor of the stand-alone output frequency divider. Conversely, increasing the feedback divisor is shown to magnify SETs propagating through the closed-loop PLL.</abstract><pub>IEEE</pub><doi>10.1109/TNS.2009.2033918</doi><tpages>10</tpages></addata></record> |
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| ispartof | IEEE transactions on nuclear science, 2009-12, Vol.56 (6), p.3489-3498 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Assurance Circuit simulation Circuit topology Circuits CMOS technology Displacement Error analysis Frequency conversion Frequency dividers Frequency synthesizers Gain Hardness Image analysis Integrated circuit synthesis Phase locked loops Propagation radiation effects Simulation single event effects single event transients Transient analysis |
| title | Analysis of Single-Event Transients in Integer- N Frequency Dividers and Hardness Assurance Implications for Phase-Locked Loops |
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