FPGA implementation of a Digital Front End block for a Multi-Carrier Multi-Antenna system
This paper describes a Field Programmable Gate Array (FPGA) implementation of a Digital Front End (DFE) block for a Multi-Carrier Multi-Antenna (MCMA) system. The decimation/ interpolation filters used for obtaining the required channel bandwidth are split into several low order decimation/ interpol...
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Format: | Tagungsbericht |
Sprache: | eng |
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Zusammenfassung: | This paper describes a Field Programmable Gate Array (FPGA) implementation of a Digital Front End (DFE) block for a Multi-Carrier Multi-Antenna (MCMA) system. The decimation/ interpolation filters used for obtaining the required channel bandwidth are split into several low order decimation/ interpolation stages, each of them being implemented as a polyphase filter. At the receiver, the DFE contains also a frame synchronization block and an automatic gain controller (AGC). The targeted chips are members of Virtex 2 family, area and speed result being provided for each block. |
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ISSN: | 1545-827X 2377-0678 |
DOI: | 10.1109/SMICND.2009.5336686 |