Area efficient vector multiplication for IDDT test calibration

This paper proposes an area efficient signal processing architecture to perform IDDT test calibration through vector multiplication. The design follows the field programmable array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements....

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Itskovich, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Calibration Circuit testing Computer science Current measurement Hardware Impedance measurement Probes Semiconductor device measurement Signal processing Vectors
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