Electrical modeling of Through Silicon and Package Vias

Electrical modeling of Through Silicon and Package Vias

This paper presents analytical modeling and 3D full-wave electromagnetic (EM) simulation of the bias voltage dependent semiconductor (MOS) capacitance of a Through Silicon Via (TSV). An accurate electrical model of the TSV is proposed by considering the semiconductor effects. The high-frequency elec...

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Hauptverfasser: Bandyopadhyay, T., Chatterjee, R., Daehyun Chung, Swaminathan, M., Tummala, R.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analytical models
Capacitance
Electromagnetic analysis
Electromagnetic modeling
Parametric study
Semiconductor device packaging
Signal design
Silicon
Through-silicon vias
Voltage
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Zusammenfassung:This paper presents analytical modeling and 3D full-wave electromagnetic (EM) simulation of the bias voltage dependent semiconductor (MOS) capacitance of a Through Silicon Via (TSV). An accurate electrical model of the TSV is proposed by considering the semiconductor effects. The high-frequency electrical performance of TSVs and Through-Package Vias (TPVs) are compared by means of 3D EM simulations. A parametric study is performed on TSV capacitance and design guidelines are presented for signal and power TSVs.
DOI:10.1109/3DIC.2009.5306542