High-level test generation using symbolic scheduling
A high-level test generation algorithm SWIFT is proposed which incorporates a symbolic scheduling procedure, derived from high-level synthesis applications, to resolve decision conflicts during test generation. SWIFT uses the induced fault model to generate functional tests that guarantee detection...
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| creator | Hansen, M.C. Hayes, J.P. |
| description | A high-level test generation algorithm SWIFT is proposed which incorporates a symbolic scheduling procedure, derived from high-level synthesis applications, to resolve decision conflicts during test generation. SWIFT uses the induced fault model to generate functional tests that guarantee detection of low-level structural faults. When applied to functional models of representative 74 X-series, ISCAS-85 and ISCAS-89 circuits. SWIFT produces test sequences that cover all gate-level stuck-at-faults. Surprisingly, although they are derived from a high-level functional description of the circuit under test, most of these test sequences are of provably minimal or near-minimal size. |
| doi_str_mv | 10.1109/TEST.1995.529887 |
| format | Conference Proceeding |
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SWIFT uses the induced fault model to generate functional tests that guarantee detection of low-level structural faults. When applied to functional models of representative 74 X-series, ISCAS-85 and ISCAS-89 circuits. SWIFT produces test sequences that cover all gate-level stuck-at-faults. Surprisingly, although they are derived from a high-level functional description of the circuit under test, most of these test sequences are of provably minimal or near-minimal size.</description><identifier>ISSN: 1089-3539</identifier><identifier>ISBN: 9780780329928</identifier><identifier>ISBN: 0780329929</identifier><identifier>EISSN: 2378-2250</identifier><identifier>DOI: 10.1109/TEST.1995.529887</identifier><language>eng</language><publisher>IEEE</publisher><subject>Automatic test pattern generation ; Circuit faults ; Circuit testing ; Clocks ; Electronic equipment testing ; Integrated circuit modeling ; Integrated circuit testing ; Logic testing ; Sequential analysis ; Sequential circuits</subject><ispartof>Proceedings of 1995 IEEE International Test Conference (ITC), 1995, p.586-595</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/529887$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/529887$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hansen, M.C.</creatorcontrib><creatorcontrib>Hayes, J.P.</creatorcontrib><title>High-level test generation using symbolic scheduling</title><title>Proceedings of 1995 IEEE International Test Conference (ITC)</title><addtitle>TEST</addtitle><description>A high-level test generation algorithm SWIFT is proposed which incorporates a symbolic scheduling procedure, derived from high-level synthesis applications, to resolve decision conflicts during test generation. SWIFT uses the induced fault model to generate functional tests that guarantee detection of low-level structural faults. When applied to functional models of representative 74 X-series, ISCAS-85 and ISCAS-89 circuits. SWIFT produces test sequences that cover all gate-level stuck-at-faults. Surprisingly, although they are derived from a high-level functional description of the circuit under test, most of these test sequences are of provably minimal or near-minimal size.</description><subject>Automatic test pattern generation</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Clocks</subject><subject>Electronic equipment testing</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuit testing</subject><subject>Logic testing</subject><subject>Sequential analysis</subject><subject>Sequential circuits</subject><issn>1089-3539</issn><issn>2378-2250</issn><isbn>9780780329928</isbn><isbn>0780329929</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj01rwzAQREU_oG6ae-lJf8DuamUh7bGEtCkEeqh7DpK9dlQcp1hOIf--hhQGBt5hHiPEo4JCKaDnav1ZFYrIFAbJOXslMtTW5YgGrsWSrIM5GonQ3YhMgaNcG0134j6lbwAEg5CJchO7fd7zL_dy4jTJjgce_RSPgzylOHQynQ_h2MdapnrPzamf2YO4bX2fePnfC_H1uq5Wm3z78fa-etnmUVmcZh15AoAQCH1AbVTrnDJaUdlAWwfPbFtyUNYlqOBKA3WjySAGryx7oxfi6bIbmXn3M8aDH8-7y1_9B53yRp4</recordid><startdate>1995</startdate><enddate>1995</enddate><creator>Hansen, M.C.</creator><creator>Hayes, J.P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1995</creationdate><title>High-level test generation using symbolic scheduling</title><author>Hansen, M.C. ; Hayes, J.P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-359a9000bb92ab2351f88153194d0fcbaee7f9804c401b8450cd39522ba17ea53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Automatic test pattern generation</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Clocks</topic><topic>Electronic equipment testing</topic><topic>Integrated circuit modeling</topic><topic>Integrated circuit testing</topic><topic>Logic testing</topic><topic>Sequential analysis</topic><topic>Sequential circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Hansen, M.C.</creatorcontrib><creatorcontrib>Hayes, J.P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEL</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hansen, M.C.</au><au>Hayes, J.P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High-level test generation using symbolic scheduling</atitle><btitle>Proceedings of 1995 IEEE International Test Conference (ITC)</btitle><stitle>TEST</stitle><date>1995</date><risdate>1995</risdate><spage>586</spage><epage>595</epage><pages>586-595</pages><issn>1089-3539</issn><eissn>2378-2250</eissn><isbn>9780780329928</isbn><isbn>0780329929</isbn><abstract>A high-level test generation algorithm SWIFT is proposed which incorporates a symbolic scheduling procedure, derived from high-level synthesis applications, to resolve decision conflicts during test generation. SWIFT uses the induced fault model to generate functional tests that guarantee detection of low-level structural faults. When applied to functional models of representative 74 X-series, ISCAS-85 and ISCAS-89 circuits. SWIFT produces test sequences that cover all gate-level stuck-at-faults. Surprisingly, although they are derived from a high-level functional description of the circuit under test, most of these test sequences are of provably minimal or near-minimal size.</abstract><pub>IEEE</pub><doi>10.1109/TEST.1995.529887</doi><tpages>10</tpages></addata></record> |
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| ispartof | Proceedings of 1995 IEEE International Test Conference (ITC), 1995, p.586-595 |
| issn | 1089-3539 2378-2250 |
| language | eng |
| recordid | cdi_ieee_primary_529887 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Automatic test pattern generation Circuit faults Circuit testing Clocks Electronic equipment testing Integrated circuit modeling Integrated circuit testing Logic testing Sequential analysis Sequential circuits |
| title | High-level test generation using symbolic scheduling |
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