Systolic array processors for 2D IIR spatio-temporal beamforming wave-digital filters (WDFs)
A systolic-array FPGA processor is proposed for implementing 2D IIR frequency-planar-beam wave digital filters (WDFs) to achieve directional enhancement of propagating broadband plane-waves based on their directions of arrival. The architecture is based on a passive LC ladder prototype network and h...
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| creator | Madanayake, H.L.P.A. Bruton, L.T. |
| description | A systolic-array FPGA processor is proposed for implementing 2D IIR frequency-planar-beam wave digital filters (WDFs) to achieve directional enhancement of propagating broadband plane-waves based on their directions of arrival. The architecture is based on a passive LC ladder prototype network and has a high-throughput of one-frame-per-clock-cycle. The structural similarity between the 2D WDF, the 2D analog prototype and the proposed implementation leads to a massively-parallel realization. An example is provided of an implementation on a Xilinx Virtex-4 Sx35-10ff668 FPGA. |
| doi_str_mv | 10.1109/PACRIM.2009.5291398 |
| format | Conference Proceeding |
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An example is provided of an implementation on a Xilinx Virtex-4 Sx35-10ff668 FPGA.</description><subject>Array signal processing</subject><subject>Computer architecture</subject><subject>Digital filters</subject><subject>Field programmable gate arrays</subject><subject>Frequency</subject><subject>IIR filters</subject><subject>Prototypes</subject><subject>Sensor arrays</subject><subject>Spatiotemporal phenomena</subject><subject>Systolic arrays</subject><issn>1555-5798</issn><issn>2154-5952</issn><isbn>9781424445608</isbn><isbn>1424445604</isbn><isbn>1424445612</isbn><isbn>9781424445615</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kDtPwzAYRc2jEqH0F3TxCIOLP78Sj1VLIVIRqIBYkCo7cSqjhER2BMq_JxLlLnc4One4CM2BLgCovn1ernb544JRqheSaeA6O0GXIJgQQipgpyhhIAWRWrIzNNNp9s9odo4SkFISmepsghJNiZISBL1Asxg_6RghOWU8QR8vQ-zb2hfYhGAG3IW2cDG2IeKqDZitcZ7vcOxM71vSu6Zrg6mxdaYZceO_DvjHfDtS-oPvR1D5uneje_2-3sSbKzSpTB3d7NhT9La5e109kO3Tfb5abomHVPZE88wKzjUvlEvLjAsquFVpqQpGrTVQmKICSEWlOTWVKUvrtFIWjBBMgnN8iuZ_u945t--Cb0wY9sfT-C95M1qS</recordid><startdate>200908</startdate><enddate>200908</enddate><creator>Madanayake, H.L.P.A.</creator><creator>Bruton, L.T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200908</creationdate><title>Systolic array processors for 2D IIR spatio-temporal beamforming wave-digital filters (WDFs)</title><author>Madanayake, H.L.P.A. ; Bruton, L.T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-938b43393c6e7d834043b67d6c20bba1cacf1174f930afaddbe966b1a44251ee3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Array signal processing</topic><topic>Computer architecture</topic><topic>Digital filters</topic><topic>Field programmable gate arrays</topic><topic>Frequency</topic><topic>IIR filters</topic><topic>Prototypes</topic><topic>Sensor arrays</topic><topic>Spatiotemporal phenomena</topic><topic>Systolic arrays</topic><toplevel>online_resources</toplevel><creatorcontrib>Madanayake, H.L.P.A.</creatorcontrib><creatorcontrib>Bruton, L.T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Madanayake, H.L.P.A.</au><au>Bruton, L.T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Systolic array processors for 2D IIR spatio-temporal beamforming wave-digital filters (WDFs)</atitle><btitle>2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing</btitle><stitle>PACRIM</stitle><date>2009-08</date><risdate>2009</risdate><spage>47</spage><epage>52</epage><pages>47-52</pages><issn>1555-5798</issn><eissn>2154-5952</eissn><isbn>9781424445608</isbn><isbn>1424445604</isbn><eisbn>1424445612</eisbn><eisbn>9781424445615</eisbn><abstract>A systolic-array FPGA processor is proposed for implementing 2D IIR frequency-planar-beam wave digital filters (WDFs) to achieve directional enhancement of propagating broadband plane-waves based on their directions of arrival. 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| ispartof | 2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2009, p.47-52 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Array signal processing Computer architecture Digital filters Field programmable gate arrays Frequency IIR filters Prototypes Sensor arrays Spatiotemporal phenomena Systolic arrays |
| title | Systolic array processors for 2D IIR spatio-temporal beamforming wave-digital filters (WDFs) |
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