Shared resources high-level modeling in embedded systems using virtual nodes

The increasing complexity of system-on-chip design and shorter time to market constraints has stimulated systems designers to investigate performance characteristics of the final system implementation in the early design stages, by means of modeling the design at a high level of abstraction. This pa...

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Bibliographische Detailangaben

Hauptverfasser:	Jaber, C., Kanstein, A., Apvrille, L., Baghdadi, A., Pacalet, R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analytical models Delay Embedded system Engineering Sciences Performance analysis Scheduling System performance System-on-a-chip Telecommunications Time to market Unified modeling language
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