Shared resources high-level modeling in embedded systems using virtual nodes
The increasing complexity of system-on-chip design and shorter time to market constraints has stimulated systems designers to investigate performance characteristics of the final system implementation in the early design stages, by means of modeling the design at a high level of abstraction. This pa...
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| creator | Jaber, C. Kanstein, A. Apvrille, L. Baghdadi, A. Pacalet, R. |
| description | The increasing complexity of system-on-chip design and shorter time to market constraints has stimulated systems designers to investigate performance characteristics of the final system implementation in the early design stages, by means of modeling the design at a high level of abstraction. This paper presents the virtual node concept for modeling the shared resources of a system-on-chip, therefore specifically dedicated to the study of the impact of shared resources contention on the overall system's performance, which is often defined by concurrent use cases. The overall approach is based on using a specific UML modeling profile and a SystemC-based simulator to execute models and analyze their performance. |
| doi_str_mv | 10.1109/NEWCAS.2009.5290506 |
| format | Conference Proceeding |
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| identifier | ISBN: 9781424445738 |
| ispartof | 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, 2009, p.1-4 |
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| language | eng |
| recordid | cdi_ieee_primary_5290506 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analytical models Delay Embedded system Engineering Sciences Performance analysis Scheduling System performance System-on-a-chip Telecommunications Time to market Unified modeling language |
| title | Shared resources high-level modeling in embedded systems using virtual nodes |
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