Insights into wideband fractional All-Digital PLLs for RF applications

Technology scaling and large-scale integration make the operating environment increasingly hostile for traditional analog design. In the area of frequency synthesis, All-Digital PLLs (ADPLLs) provide an attractive alternative to conventional PLLs: their wide programmability allows for multistandard application, and a digital intensive design means easy reconfigurability and shorter design cycles. However, wideband fractional ADPLLs come with a different set of problems, principally in-band spurious tones. Techniques to suppress spurious tones would eliminate a major obstacle for ADPLLs' widespread proliferation into wireless RF applications. In this paper we first describe the evolution from the analog PLL to the divider-less ADPLL, of major interest for RF to date, then develop a model to predict location and level of spurs. Finally, we present a technique for spur reduction by means of digital calibration. Validation is performed through experiments on an ADPLL fabricated in 65 nm digital CMOS.