A New SRAM Cell Design for Both Power and Performance Efficiency
This paper presents a new six-transistor static random access memory (6 T SRAM) cell with significantly reduced power consumption that achieves high read and write performance. Unlike traditional 6 T SRAMs, this study proposes an asymmetric 6 T SRAM which uses a single line to implement read or writ...
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| creator | Yen-Ting Chiang Yen-Jen Chang |
| description | This paper presents a new six-transistor static random access memory (6 T SRAM) cell with significantly reduced power consumption that achieves high read and write performance. Unlike traditional 6 T SRAMs, this study proposes an asymmetric 6 T SRAM which uses a single line to implement read or write operations without reducing performance. This design not only reduces power consumption, but also improves read and write performance. The proposed SRAM design is implemented with UMC 90 nm, 1.0-V supply voltage CMOS technologies. Compared to conventional six transistor SRAM cells, the new cell design successfully power consumption by 40-60%. In addition, the read and write performance has been improved by 13.6% and 41.2%. |
| doi_str_mv | 10.1109/MTDT.2009.13 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5279850</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5279850</ieee_id><sourcerecordid>5279850</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-1fbf482e3f7d573e94ddcd79df9f32a47cb2f7a14dbbebb6d44f7e915e7d86983</originalsourceid><addsrcrecordid>eNotj0tLw0AUhQe1YKzZuXMzfyB1nrlzd8a0PqDVonVdkswdHWkTSQql_96Kns2BD84Hh7ErKSZSCrxZrKariRICJ1KfsERZyDOU1pyyFMEJyNFqQMAzlkjhIDPOqhG7-F2gyKXDc5YOw5c4xqocQSXstuDPtOdvr8WCl7TZ8CkN8aPloev5Xbf75MtuTz2vWs-X1B_ptmob4rMQYhOpbQ6XbBSqzUDpf4_Z-_1sVT5m85eHp7KYZ1GC3WUy1ME4RTqAt6AJjfeNB_QBg1aVgaZWASppfF1TXefemAB0PEfgXY5Oj9n1nzcS0fq7j9uqP6ytAnRW6B8AIEys</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A New SRAM Cell Design for Both Power and Performance Efficiency</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Yen-Ting Chiang ; Yen-Jen Chang</creator><creatorcontrib>Yen-Ting Chiang ; Yen-Jen Chang</creatorcontrib><description>This paper presents a new six-transistor static random access memory (6 T SRAM) cell with significantly reduced power consumption that achieves high read and write performance. Unlike traditional 6 T SRAMs, this study proposes an asymmetric 6 T SRAM which uses a single line to implement read or write operations without reducing performance. This design not only reduces power consumption, but also improves read and write performance. The proposed SRAM design is implemented with UMC 90 nm, 1.0-V supply voltage CMOS technologies. Compared to conventional six transistor SRAM cells, the new cell design successfully power consumption by 40-60%. In addition, the read and write performance has been improved by 13.6% and 41.2%.</description><identifier>ISSN: 1087-4852</identifier><identifier>ISBN: 9780769537979</identifier><identifier>ISBN: 0769537979</identifier><identifier>EISSN: 2576-9154</identifier><identifier>DOI: 10.1109/MTDT.2009.13</identifier><identifier>LCCN: 2009906189</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuits ; CMOS technology ; Computer science ; Conferences ; Energy consumption ; Gate leakage ; high performance ; low power ; Power engineering and energy ; Random access memory ; Read-write memory ; sram ; Threshold voltage</subject><ispartof>2009 IEEE International Workshop on Memory Technology, Design, and Testing, 2009, p.13-19</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5279850$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5279850$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yen-Ting Chiang</creatorcontrib><creatorcontrib>Yen-Jen Chang</creatorcontrib><title>A New SRAM Cell Design for Both Power and Performance Efficiency</title><title>2009 IEEE International Workshop on Memory Technology, Design, and Testing</title><addtitle>MTDT</addtitle><description>This paper presents a new six-transistor static random access memory (6 T SRAM) cell with significantly reduced power consumption that achieves high read and write performance. Unlike traditional 6 T SRAMs, this study proposes an asymmetric 6 T SRAM which uses a single line to implement read or write operations without reducing performance. This design not only reduces power consumption, but also improves read and write performance. The proposed SRAM design is implemented with UMC 90 nm, 1.0-V supply voltage CMOS technologies. Compared to conventional six transistor SRAM cells, the new cell design successfully power consumption by 40-60%. In addition, the read and write performance has been improved by 13.6% and 41.2%.</description><subject>Circuits</subject><subject>CMOS technology</subject><subject>Computer science</subject><subject>Conferences</subject><subject>Energy consumption</subject><subject>Gate leakage</subject><subject>high performance</subject><subject>low power</subject><subject>Power engineering and energy</subject><subject>Random access memory</subject><subject>Read-write memory</subject><subject>sram</subject><subject>Threshold voltage</subject><issn>1087-4852</issn><issn>2576-9154</issn><isbn>9780769537979</isbn><isbn>0769537979</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0tLw0AUhQe1YKzZuXMzfyB1nrlzd8a0PqDVonVdkswdHWkTSQql_96Kns2BD84Hh7ErKSZSCrxZrKariRICJ1KfsERZyDOU1pyyFMEJyNFqQMAzlkjhIDPOqhG7-F2gyKXDc5YOw5c4xqocQSXstuDPtOdvr8WCl7TZ8CkN8aPloev5Xbf75MtuTz2vWs-X1B_ptmob4rMQYhOpbQ6XbBSqzUDpf4_Z-_1sVT5m85eHp7KYZ1GC3WUy1ME4RTqAt6AJjfeNB_QBg1aVgaZWASppfF1TXefemAB0PEfgXY5Oj9n1nzcS0fq7j9uqP6ytAnRW6B8AIEys</recordid><startdate>200908</startdate><enddate>200908</enddate><creator>Yen-Ting Chiang</creator><creator>Yen-Jen Chang</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200908</creationdate><title>A New SRAM Cell Design for Both Power and Performance Efficiency</title><author>Yen-Ting Chiang ; Yen-Jen Chang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-1fbf482e3f7d573e94ddcd79df9f32a47cb2f7a14dbbebb6d44f7e915e7d86983</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Circuits</topic><topic>CMOS technology</topic><topic>Computer science</topic><topic>Conferences</topic><topic>Energy consumption</topic><topic>Gate leakage</topic><topic>high performance</topic><topic>low power</topic><topic>Power engineering and energy</topic><topic>Random access memory</topic><topic>Read-write memory</topic><topic>sram</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Yen-Ting Chiang</creatorcontrib><creatorcontrib>Yen-Jen Chang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yen-Ting Chiang</au><au>Yen-Jen Chang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A New SRAM Cell Design for Both Power and Performance Efficiency</atitle><btitle>2009 IEEE International Workshop on Memory Technology, Design, and Testing</btitle><stitle>MTDT</stitle><date>2009-08</date><risdate>2009</risdate><spage>13</spage><epage>19</epage><pages>13-19</pages><issn>1087-4852</issn><eissn>2576-9154</eissn><isbn>9780769537979</isbn><isbn>0769537979</isbn><abstract>This paper presents a new six-transistor static random access memory (6 T SRAM) cell with significantly reduced power consumption that achieves high read and write performance. Unlike traditional 6 T SRAMs, this study proposes an asymmetric 6 T SRAM which uses a single line to implement read or write operations without reducing performance. This design not only reduces power consumption, but also improves read and write performance. The proposed SRAM design is implemented with UMC 90 nm, 1.0-V supply voltage CMOS technologies. Compared to conventional six transistor SRAM cells, the new cell design successfully power consumption by 40-60%. In addition, the read and write performance has been improved by 13.6% and 41.2%.</abstract><pub>IEEE</pub><doi>10.1109/MTDT.2009.13</doi><tpages>7</tpages></addata></record> |
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| identifier | ISSN: 1087-4852 |
| ispartof | 2009 IEEE International Workshop on Memory Technology, Design, and Testing, 2009, p.13-19 |
| issn | 1087-4852 2576-9154 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits CMOS technology Computer science Conferences Energy consumption Gate leakage high performance low power Power engineering and energy Random access memory Read-write memory sram Threshold voltage |
| title | A New SRAM Cell Design for Both Power and Performance Efficiency |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T18%3A06%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20New%20SRAM%20Cell%20Design%20for%20Both%20Power%20and%20Performance%20Efficiency&rft.btitle=2009%20IEEE%20International%20Workshop%20on%20Memory%20Technology,%20Design,%20and%20Testing&rft.au=Yen-Ting%20Chiang&rft.date=2009-08&rft.spage=13&rft.epage=19&rft.pages=13-19&rft.issn=1087-4852&rft.eissn=2576-9154&rft.isbn=9780769537979&rft.isbn_list=0769537979&rft_id=info:doi/10.1109/MTDT.2009.13&rft_dat=%3Cieee_6IE%3E5279850%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5279850&rfr_iscdi=true |