Achieving low-cost high-reliability computation through redundant parallel processing

This paper presents a reconfigurable parallel architecture comprising an FPGA backbone and multiple processing nodes connected in a redundant array architecture and constructed mainly from low-cost commercial components. The reconfigurability of the backbone aids in allowing the system to operate as...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	McLoughlin, I.V., Bretschneider, T.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Concurrent computing Embedded computing Fault tolerant systems Field programmable gate arrays Parallel architectures Parallel processing Power system reliability Redundancy Spine
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!