Achieving low-cost high-reliability computation through redundant parallel processing
This paper presents a reconfigurable parallel architecture comprising an FPGA backbone and multiple processing nodes connected in a redundant array architecture and constructed mainly from low-cost commercial components. The reconfigurability of the backbone aids in allowing the system to operate as...
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| creator | McLoughlin, I.V. Bretschneider, T. |
| description | This paper presents a reconfigurable parallel architecture comprising an FPGA backbone and multiple processing nodes connected in a redundant array architecture and constructed mainly from low-cost commercial components. The reconfigurability of the backbone aids in allowing the system to operate as a fault-tolerant cluster utilising the principle of reliability through redundancy. Although initially designed for space-borne on-board processing of satellite imagery, the system combines the advantages of powerful computational resources with simplified software development. This makes the computer a useful general-purpose embedded processing block for critical computational tasks where fault-tolerance and high processing capabilities are required. |
| doi_str_mv | 10.1109/ICOCI.2006.5276450 |
| format | Conference Proceeding |
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This makes the computer a useful general-purpose embedded processing block for critical computational tasks where fault-tolerance and high processing capabilities are required.</description><subject>Computer architecture</subject><subject>Concurrent computing</subject><subject>Embedded computing</subject><subject>Fault tolerant systems</subject><subject>Field programmable gate arrays</subject><subject>Parallel architectures</subject><subject>Parallel processing</subject><subject>Power system reliability</subject><subject>Redundancy</subject><subject>Spine</subject><issn>2166-5710</issn><isbn>1424402190</isbn><isbn>9781424402199</isbn><isbn>9781424402205</isbn><isbn>1424402204</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2006</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkMtOwzAURI2gElD6A7DxD6RcP25sL6uIR6VK3ZR15TpOY-QmkeOC-vdEorOZmcWcxRDyzGDJGJjXdbWt1ksOUC6Rq1Ii3JCFUZpJLiVwDnhLHq-FGbgjD5yVZYGKwWzK085wMHhPFuP4DZMkyonzQL5Wrg3-J3RHGvvfwvVjpm04tkXyMdhDiCFfqOtPwznbHPqO5jb152NLk6_PXW27TAebbIw-0iH1zo_jxHois8bG0S-uPie797dd9Vlsth_rarUpgoFcaAG6dBy1ZMrZpkYhBK9rg85rKVAZK4zQFh0qbwRT4A_ONQ2aBu2h1F7Mycs_Nnjv90MKJ5su--tB4g9vL1b_</recordid><startdate>200606</startdate><enddate>200606</enddate><creator>McLoughlin, I.V.</creator><creator>Bretschneider, T.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200606</creationdate><title>Achieving low-cost high-reliability computation through redundant parallel processing</title><author>McLoughlin, I.V. ; Bretschneider, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-83086c258417cafd53332dd95ce843579a3938a5c57e93170ebccff59f5ab68e3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Computer architecture</topic><topic>Concurrent computing</topic><topic>Embedded computing</topic><topic>Fault tolerant systems</topic><topic>Field programmable gate arrays</topic><topic>Parallel architectures</topic><topic>Parallel processing</topic><topic>Power system reliability</topic><topic>Redundancy</topic><topic>Spine</topic><toplevel>online_resources</toplevel><creatorcontrib>McLoughlin, I.V.</creatorcontrib><creatorcontrib>Bretschneider, T.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>McLoughlin, I.V.</au><au>Bretschneider, T.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Achieving low-cost high-reliability computation through redundant parallel processing</atitle><btitle>2006 International Conference on Computing & Informatics</btitle><stitle>ICOCI</stitle><date>2006-06</date><risdate>2006</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><issn>2166-5710</issn><isbn>1424402190</isbn><isbn>9781424402199</isbn><eisbn>9781424402205</eisbn><eisbn>1424402204</eisbn><abstract>This paper presents a reconfigurable parallel architecture comprising an FPGA backbone and multiple processing nodes connected in a redundant array architecture and constructed mainly from low-cost commercial components. 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| ispartof | 2006 International Conference on Computing & Informatics, 2006, p.1-6 |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Computer architecture Concurrent computing Embedded computing Fault tolerant systems Field programmable gate arrays Parallel architectures Parallel processing Power system reliability Redundancy Spine |
| title | Achieving low-cost high-reliability computation through redundant parallel processing |
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