A unified cellular array for multiplication, division and square root
A unified fast, small-area processor capable of executing multiplication, division and square-root operations, all starting from MSD is proposed. Unlike the existing designs which require both addition and subtraction operations, and complicated estimator for DIV/SQRT result digits, the proposed des...
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| creator | San-Gee Chen Chieh-Chih Li |
| description | A unified fast, small-area processor capable of executing multiplication, division and square-root operations, all starting from MSD is proposed. Unlike the existing designs which require both addition and subtraction operations, and complicated estimator for DIV/SQRT result digits, the proposed design consists of only addition operations and no complicated estimator. By taking negative absolute values of partial remainders, the algorithm breaks the sequential tie between residue sign detection and the next remainder update operations. As such, these two operations can be parallely and independently performed. The proposed architecture has smaller area and more regular structure than the known designs. |
| doi_str_mv | 10.1109/VLSISP.1995.527524 |
| format | Conference Proceeding |
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Unlike the existing designs which require both addition and subtraction operations, and complicated estimator for DIV/SQRT result digits, the proposed design consists of only addition operations and no complicated estimator. By taking negative absolute values of partial remainders, the algorithm breaks the sequential tie between residue sign detection and the next remainder update operations. As such, these two operations can be parallely and independently performed. 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The proposed architecture has smaller area and more regular structure than the known designs.</description><subject>Algorithm design and analysis</subject><subject>Arithmetic</subject><subject>Circuits</subject><subject>Communication system control</subject><subject>Data communication</subject><subject>Delay</subject><subject>Digital signal processing</subject><subject>Hardware</subject><subject>Signal processing algorithms</subject><subject>Throughput</subject><isbn>9780780326125</isbn><isbn>0780326121</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jtEKgjAYhQcRFOULePU_QNk2W7rLCKOgi8DoVoZO-GM62zTo7RPqusOB78B3cwgJGY0Yo3Jzv-Tn_BoxKUUkeCL4dkICmaR0bMx3jIsZCbx_0DFCpDKhc5LtYWixRl1BqY0ZjHKgnFNvqK2DZjA9dgZL1aNtV1DhC_24QLUV-OegnAZnbb8k01oZr4MfFyQ8ZrfDaY1a66Jz2Cj3Lr6f4r_yA4MuO6Q</recordid><startdate>1995</startdate><enddate>1995</enddate><creator>San-Gee Chen</creator><creator>Chieh-Chih Li</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1995</creationdate><title>A unified cellular array for multiplication, division and square root</title><author>San-Gee Chen ; Chieh-Chih Li</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_5275243</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Algorithm design and analysis</topic><topic>Arithmetic</topic><topic>Circuits</topic><topic>Communication system control</topic><topic>Data communication</topic><topic>Delay</topic><topic>Digital signal processing</topic><topic>Hardware</topic><topic>Signal processing algorithms</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>San-Gee Chen</creatorcontrib><creatorcontrib>Chieh-Chih Li</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>San-Gee Chen</au><au>Chieh-Chih Li</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A unified cellular array for multiplication, division and square root</atitle><btitle>VLSI Signal Processing, VIII</btitle><stitle>VLSISP</stitle><date>1995</date><risdate>1995</risdate><spage>533</spage><epage>541</epage><pages>533-541</pages><isbn>9780780326125</isbn><isbn>0780326121</isbn><abstract>A unified fast, small-area processor capable of executing multiplication, division and square-root operations, all starting from MSD is proposed. Unlike the existing designs which require both addition and subtraction operations, and complicated estimator for DIV/SQRT result digits, the proposed design consists of only addition operations and no complicated estimator. By taking negative absolute values of partial remainders, the algorithm breaks the sequential tie between residue sign detection and the next remainder update operations. As such, these two operations can be parallely and independently performed. The proposed architecture has smaller area and more regular structure than the known designs.</abstract><pub>IEEE</pub><doi>10.1109/VLSISP.1995.527524</doi></addata></record> |
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| identifier | ISBN: 9780780326125 |
| ispartof | VLSI Signal Processing, VIII, 1995, p.533-541 |
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| language | eng |
| recordid | cdi_ieee_primary_527524 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Arithmetic Circuits Communication system control Data communication Delay Digital signal processing Hardware Signal processing algorithms Throughput |
| title | A unified cellular array for multiplication, division and square root |
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