Some simulated properties of the pseudostructure of a floating gate MOS transistor

Some simulated properties of the pseudostructure of a floating gate MOS transistor

The floating gate technology is widely used as a memory element in digital circuits and as a novel memory element in analogue technology. In this work we prepare the basis for on-chip implementation of a Cellular Neural Network (CNN). For this purpose we investigate the features of a pseudo-floating...

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Bibliographische Detailangaben
Hauptverfasser: Durackova, D., Krajmer, M., Racko, J., Breza, J., Kadlecikova, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Cellular neural networks
Digital circuits
Doping
Information technology
Microelectronics
MOSFETs
Network-on-a-chip
Nonvolatile memory
Threshold voltage
Virtual colonoscopy
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Beschreibung
Zusammenfassung:The floating gate technology is widely used as a memory element in digital circuits and as a novel memory element in analogue technology. In this work we prepare the basis for on-chip implementation of a Cellular Neural Network (CNN). For this purpose we investigate the features of a pseudo-floating gate transistor introduced in [1]. After simulating the structure by T-CAD tool we designed a behavioural model in SPICE that could be implemented into CADENCE design tool.
ISSN:2161-2528
DOI:10.1109/ISSE.2009.5207000