Real-time H.264 encoder implementation on a low-power digital signal processor
This paper presents a real-time H.264/AVC baseline profile video encoder. The encoder hardware is implemented using a cost-effective, low-power ADI Blackin-561 DSP and related peripherals for real-time video capturing, coding and streaming. The encoder software is developed using a two-stage pipelin...
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creator | Ming-Jiang Yang Jo-Yew Tham Rahardja, S. Da-Jun Wu |
description | This paper presents a real-time H.264/AVC baseline profile video encoder. The encoder hardware is implemented using a cost-effective, low-power ADI Blackin-561 DSP and related peripherals for real-time video capturing, coding and streaming. The encoder software is developed using a two-stage pipelining framework for efficient parallel video data encoding. A synchronization mechanism with shared memory semaphores is used to schedule the hardware processes and software procedures to acquire the real-time encoding performance. Techniques for reducing the execution time in both stages are also described in this paper. Performance evaluation results verified that the encoder is capable of performing real-time encoding of CIF-resolution and medium-motion VGA-resolution videos, while maintaining good video quality. |
doi_str_mv | 10.1109/ICME.2009.5202703 |
format | Conference Proceeding |
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The encoder hardware is implemented using a cost-effective, low-power ADI Blackin-561 DSP and related peripherals for real-time video capturing, coding and streaming. The encoder software is developed using a two-stage pipelining framework for efficient parallel video data encoding. A synchronization mechanism with shared memory semaphores is used to schedule the hardware processes and software procedures to acquire the real-time encoding performance. Techniques for reducing the execution time in both stages are also described in this paper. Performance evaluation results verified that the encoder is capable of performing real-time encoding of CIF-resolution and medium-motion VGA-resolution videos, while maintaining good video quality.</description><subject>Automatic voltage control</subject><subject>Digital signal processing</subject><subject>Digital signal processors</subject><subject>embedded media processing</subject><subject>Encoding</subject><subject>H.264</subject><subject>Hardware</subject><subject>multicore DSP</subject><subject>Performance evaluation</subject><subject>Pipeline processing</subject><subject>real-time encoder</subject><subject>scheduling</subject><subject>Software performance</subject><subject>Streaming media</subject><subject>Video sharing</subject><issn>1945-7871</issn><issn>1945-788X</issn><isbn>9781424442904</isbn><isbn>1424442907</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kM1Kw0AUhQd_wFLzAOImL5B4b-bOJLOUUG2hKoiCuzLJ3Ckj-SMJFN_egMXDgW_xwVkcIe4QUkQwD7vyZZNmACZVGWQ5yAuxQkMqyYvi61JEJi-QMiLKDNDVv8vxRkTT9A1LSElEvRKv72ybZA4tx9s00xRzV_eOxzi0Q8Mtd7OdQ9_FS23c9Kdk6E-LdeEYZtvEUzh2C4axr3ma-vFWXHvbTByduRafT5uPcpvs35535eM-CZirOfG6qgpjQHnni1p7g6Sp8MqzBeugMs5JAgRXoVFUKZQ5mkq7mrRlllquxf3fbmDmwzCG1o4_h_Mb8hc5RlDv</recordid><startdate>200906</startdate><enddate>200906</enddate><creator>Ming-Jiang Yang</creator><creator>Jo-Yew Tham</creator><creator>Rahardja, S.</creator><creator>Da-Jun Wu</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200906</creationdate><title>Real-time H.264 encoder implementation on a low-power digital signal processor</title><author>Ming-Jiang Yang ; Jo-Yew Tham ; Rahardja, S. ; Da-Jun Wu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-f6bb89905fdf8c6f914648f5fea0ad0b9dd34010db1954b513719b6dc46aee363</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Automatic voltage control</topic><topic>Digital signal processing</topic><topic>Digital signal processors</topic><topic>embedded media processing</topic><topic>Encoding</topic><topic>H.264</topic><topic>Hardware</topic><topic>multicore DSP</topic><topic>Performance evaluation</topic><topic>Pipeline processing</topic><topic>real-time encoder</topic><topic>scheduling</topic><topic>Software performance</topic><topic>Streaming media</topic><topic>Video sharing</topic><toplevel>online_resources</toplevel><creatorcontrib>Ming-Jiang Yang</creatorcontrib><creatorcontrib>Jo-Yew Tham</creatorcontrib><creatorcontrib>Rahardja, S.</creatorcontrib><creatorcontrib>Da-Jun Wu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ming-Jiang Yang</au><au>Jo-Yew Tham</au><au>Rahardja, S.</au><au>Da-Jun Wu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Real-time H.264 encoder implementation on a low-power digital signal processor</atitle><btitle>2009 IEEE International Conference on Multimedia and Expo</btitle><stitle>ICME</stitle><date>2009-06</date><risdate>2009</risdate><spage>1150</spage><epage>1153</epage><pages>1150-1153</pages><issn>1945-7871</issn><eissn>1945-788X</eissn><isbn>9781424442904</isbn><isbn>1424442907</isbn><abstract>This paper presents a real-time H.264/AVC baseline profile video encoder. The encoder hardware is implemented using a cost-effective, low-power ADI Blackin-561 DSP and related peripherals for real-time video capturing, coding and streaming. The encoder software is developed using a two-stage pipelining framework for efficient parallel video data encoding. A synchronization mechanism with shared memory semaphores is used to schedule the hardware processes and software procedures to acquire the real-time encoding performance. Techniques for reducing the execution time in both stages are also described in this paper. Performance evaluation results verified that the encoder is capable of performing real-time encoding of CIF-resolution and medium-motion VGA-resolution videos, while maintaining good video quality.</abstract><pub>IEEE</pub><doi>10.1109/ICME.2009.5202703</doi><tpages>4</tpages></addata></record> |
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identifier | ISSN: 1945-7871 |
ispartof | 2009 IEEE International Conference on Multimedia and Expo, 2009, p.1150-1153 |
issn | 1945-7871 1945-788X |
language | eng |
recordid | cdi_ieee_primary_5202703 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Automatic voltage control Digital signal processing Digital signal processors embedded media processing Encoding H.264 Hardware multicore DSP Performance evaluation Pipeline processing real-time encoder scheduling Software performance Streaming media Video sharing |
title | Real-time H.264 encoder implementation on a low-power digital signal processor |
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