Optimization of lossless audio decoders on a class of embedded systems with two cores
Increasing demand for high quality audio/video content put a great pressure on A/V codec complexity. On the other side, low-end devices demands low cost platforms. In this paper we present methodology for optimization of lossless audio decoders on a dual core DSP-s. In addition to the common techniq...
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| creator | Tadic, M. Sajic, D. Kovacevic, J. |
| description | Increasing demand for high quality audio/video content put a great pressure on A/V codec complexity. On the other side, low-end devices demands low cost platforms. In this paper we present methodology for optimization of lossless audio decoders on a dual core DSP-s. In addition to the common techniques such as: instruction parallelization and buffer reusability, we describe generalized splitting algorithm technique, exploiting features of embedded system. The methodology of proposed algorithm is illustrated on CS4953xx dual core processor, tested in simulator and verified in real time systems (AVRs, Blu-Ray Players). Estimated 180 MIPS for audio decoder was split on 140 MIPS on a first core and 55 MIPS on a second core, providing MIPS vise optimal solution for entire system. |
| doi_str_mv | 10.1109/ICDSP.2009.5201061 |
| format | Conference Proceeding |
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| ispartof | 2009 16th International Conference on Digital Signal Processing, 2009, p.1-6 |
| issn | 1546-1874 2165-3577 |
| language | eng |
| recordid | cdi_ieee_primary_5201061 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Codecs Decoding Digital signal processing Digital signal processing chips DSP dual core Embedded system Hardware hw/sw optimization Lossless audio decoder Optimization methods parallelization Signal processing algorithms Testing |
| title | Optimization of lossless audio decoders on a class of embedded systems with two cores |
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