Optimized Scalable Hardware Architecture for Modular Addition and Subtraction in Dual-Field

Modular addition and subtraction are applied in every public key cryptography (PKC), such as RSA and ECC. But they are time consuming operations with delay of long carry and borrow propagations when the operands are great numbers. An optimized scalable and unified hardware architecture is proposed i...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Qin Fan, Yang Xiao-hui, Dai Zi-bin
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arithmetic Clocks CMOS technology Elliptic curve cryptography Frequency Galois fields Hardware Modular Addition Modular Subtraction Polynomials Propagation delay Public Key Cryptograph Public key cryptography
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