Reliability for manufacturing on 45nm logic technology with high-k + metal gate transistors and Pb-free packaging

This paper addresses several key aspects of integrated reliability for the Intel 45 nm logic technology with high-K metal gate (HK + MG) transistors and Pb-free packaging. Significant changes in process architecture and materials were introduced and careful integration and manufacturing innovations were needed to meet historical expectations for transistor, defect, and package reliability. Furthermore the stability of intrinsic and defect reliability performance needed to be demonstrated. Highly accelerated TDDB and bias temperature instability (BTI) tests were implemented to enable very high sampling rates, establishing stable transistor reliability in high manufacturing volumes. Integrated product defect reliability results are presented showing that the historical correlation to yield defect density for stable manufacturing processes is maintained on this generation into an even lower fail rate regime. Similarly, volume package reliability monitor data are shown validating thermo-mechanical stability of the 1st level Pb-free package interconnect.