Fast simulation framework for subthreshold circuits

Subthreshold voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. This is beneficial in embedded applications that must run off of batteries and scavenged energy. Subthreshold operation has been proven to be very effecti...

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Hauptverfasser: Henry, M.B., Griffin, S.B., Nazhandali, L.
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description Subthreshold voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. This is beneficial in embedded applications that must run off of batteries and scavenged energy. Subthreshold operation has been proven to be very effective by several successful prototypes in the recent years, yet there is no fast and effective way for designers to estimate power and delay of a design operating in the subthreshold region. Traditional gate-level simulation tools are not set up to perform timing and power analysis in the subthreshold region and transistor level simulations are very time consuming due to the accuracy required to measure the very low levels of current. This paper presents a simulation framework that can accurately characterize a circuit from nominal voltage, all the way down into the subthreshold region. This framework uses the nominal frequency and power of a target circuit and a normalized ring oscillator curve to characterize the circuit at lower voltages. The contribution of this paper is a detailed analysis of this framework in the presence of a variety of design parameters such as bus lengths, transistor widths, etc. The simulation framework is extremely quick and accurate across a wide variety of circuits.
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5118321</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5118321</ieee_id><sourcerecordid>5118321</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-d106cfc2f78aff1af7c5241227a13d74113e7a495e83b768b210d602074f2b623</originalsourceid><addsrcrecordid>eNpFkM1Kw0AURsefgmn1BXSTF0i8985vliVYLRRcVNdlkszQ0dTITIL49hZacHUWHxw-DmP3CCUiVI_rbb3clgRQlRLRcMILNkdBQnBDRlyyjFCaAiXJq_9Bq2uWAWksBAeascxAoYSSHG7YPKUPgKNRUcb4yqYxT-Ew9XYMw1fuoz24nyF-5n6IeZqacR9d2g99l7chtlMY0y2bedsnd3fmgr2vnt7ql2Lz-ryul5sioJZj0SGo1rfktbHeo_W6lSSQSFvknRaI3GkrKukMb7QyDSF06nhMC0-NIr5gDydvcM7tvmM42Pi7O1fgf9SpSgg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Fast simulation framework for subthreshold circuits</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Henry, M.B. ; Griffin, S.B. ; Nazhandali, L.</creator><creatorcontrib>Henry, M.B. ; Griffin, S.B. ; Nazhandali, L.</creatorcontrib><description>Subthreshold voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. This is beneficial in embedded applications that must run off of batteries and scavenged energy. Subthreshold operation has been proven to be very effective by several successful prototypes in the recent years, yet there is no fast and effective way for designers to estimate power and delay of a design operating in the subthreshold region. Traditional gate-level simulation tools are not set up to perform timing and power analysis in the subthreshold region and transistor level simulations are very time consuming due to the accuracy required to measure the very low levels of current. This paper presents a simulation framework that can accurately characterize a circuit from nominal voltage, all the way down into the subthreshold region. This framework uses the nominal frequency and power of a target circuit and a normalized ring oscillator curve to characterize the circuit at lower voltages. The contribution of this paper is a detailed analysis of this framework in the presence of a variety of design parameters such as bus lengths, transistor widths, etc. The simulation framework is extremely quick and accurate across a wide variety of circuits.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 1424438276</identifier><identifier>ISBN: 9781424438273</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 1424438284</identifier><identifier>EISBN: 9781424438280</identifier><identifier>DOI: 10.1109/ISCAS.2009.5118321</identifier><identifier>LCCN: 80-646530</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analytical models ; Batteries ; Circuit simulation ; Delay effects ; Delay estimation ; Energy consumption ; Performance evaluation ; Prototypes ; Timing ; Voltage</subject><ispartof>2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.2549-2552</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5118321$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>310,311,781,785,790,791,2059,27930,54925</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5118321$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Henry, M.B.</creatorcontrib><creatorcontrib>Griffin, S.B.</creatorcontrib><creatorcontrib>Nazhandali, L.</creatorcontrib><title>Fast simulation framework for subthreshold circuits</title><title>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>Subthreshold voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. This is beneficial in embedded applications that must run off of batteries and scavenged energy. Subthreshold operation has been proven to be very effective by several successful prototypes in the recent years, yet there is no fast and effective way for designers to estimate power and delay of a design operating in the subthreshold region. Traditional gate-level simulation tools are not set up to perform timing and power analysis in the subthreshold region and transistor level simulations are very time consuming due to the accuracy required to measure the very low levels of current. This paper presents a simulation framework that can accurately characterize a circuit from nominal voltage, all the way down into the subthreshold region. This framework uses the nominal frequency and power of a target circuit and a normalized ring oscillator curve to characterize the circuit at lower voltages. The contribution of this paper is a detailed analysis of this framework in the presence of a variety of design parameters such as bus lengths, transistor widths, etc. The simulation framework is extremely quick and accurate across a wide variety of circuits.</description><subject>Analytical models</subject><subject>Batteries</subject><subject>Circuit simulation</subject><subject>Delay effects</subject><subject>Delay estimation</subject><subject>Energy consumption</subject><subject>Performance evaluation</subject><subject>Prototypes</subject><subject>Timing</subject><subject>Voltage</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424438276</isbn><isbn>9781424438273</isbn><isbn>1424438284</isbn><isbn>9781424438280</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkM1Kw0AURsefgmn1BXSTF0i8985vliVYLRRcVNdlkszQ0dTITIL49hZacHUWHxw-DmP3CCUiVI_rbb3clgRQlRLRcMILNkdBQnBDRlyyjFCaAiXJq_9Bq2uWAWksBAeascxAoYSSHG7YPKUPgKNRUcb4yqYxT-Ew9XYMw1fuoz24nyF-5n6IeZqacR9d2g99l7chtlMY0y2bedsnd3fmgr2vnt7ql2Lz-ryul5sioJZj0SGo1rfktbHeo_W6lSSQSFvknRaI3GkrKukMb7QyDSF06nhMC0-NIr5gDydvcM7tvmM42Pi7O1fgf9SpSgg</recordid><startdate>200905</startdate><enddate>200905</enddate><creator>Henry, M.B.</creator><creator>Griffin, S.B.</creator><creator>Nazhandali, L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200905</creationdate><title>Fast simulation framework for subthreshold circuits</title><author>Henry, M.B. ; Griffin, S.B. ; Nazhandali, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-d106cfc2f78aff1af7c5241227a13d74113e7a495e83b768b210d602074f2b623</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Analytical models</topic><topic>Batteries</topic><topic>Circuit simulation</topic><topic>Delay effects</topic><topic>Delay estimation</topic><topic>Energy consumption</topic><topic>Performance evaluation</topic><topic>Prototypes</topic><topic>Timing</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Henry, M.B.</creatorcontrib><creatorcontrib>Griffin, S.B.</creatorcontrib><creatorcontrib>Nazhandali, L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Henry, M.B.</au><au>Griffin, S.B.</au><au>Nazhandali, L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Fast simulation framework for subthreshold circuits</atitle><btitle>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2009-05</date><risdate>2009</risdate><spage>2549</spage><epage>2552</epage><pages>2549-2552</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424438276</isbn><isbn>9781424438273</isbn><eisbn>1424438284</eisbn><eisbn>9781424438280</eisbn><abstract>Subthreshold voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. This is beneficial in embedded applications that must run off of batteries and scavenged energy. Subthreshold operation has been proven to be very effective by several successful prototypes in the recent years, yet there is no fast and effective way for designers to estimate power and delay of a design operating in the subthreshold region. Traditional gate-level simulation tools are not set up to perform timing and power analysis in the subthreshold region and transistor level simulations are very time consuming due to the accuracy required to measure the very low levels of current. This paper presents a simulation framework that can accurately characterize a circuit from nominal voltage, all the way down into the subthreshold region. This framework uses the nominal frequency and power of a target circuit and a normalized ring oscillator curve to characterize the circuit at lower voltages. The contribution of this paper is a detailed analysis of this framework in the presence of a variety of design parameters such as bus lengths, transistor widths, etc. The simulation framework is extremely quick and accurate across a wide variety of circuits.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2009.5118321</doi><tpages>4</tpages></addata></record>
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subjects Analytical models
Batteries
Circuit simulation
Delay effects
Delay estimation
Energy consumption
Performance evaluation
Prototypes
Timing
Voltage
title Fast simulation framework for subthreshold circuits
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T10%3A48%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Fast%20simulation%20framework%20for%20subthreshold%20circuits&rft.btitle=2009%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Henry,%20M.B.&rft.date=2009-05&rft.spage=2549&rft.epage=2552&rft.pages=2549-2552&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=1424438276&rft.isbn_list=9781424438273&rft_id=info:doi/10.1109/ISCAS.2009.5118321&rft_dat=%3Cieee_6IE%3E5118321%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424438284&rft.eisbn_list=9781424438280&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5118321&rfr_iscdi=true