Design of a power-aware digital image rejection receiver
This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce th...
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creator | Cetin, E. Kale, I. Morling, R.C.S. |
description | This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits. |
doi_str_mv | 10.1109/ISCAS.2009.5117722 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5117722</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5117722</ieee_id><sourcerecordid>5117722</sourcerecordid><originalsourceid>FETCH-LOGICAL-i219t-d186674f6bf7f7529b5f8f0586b6e0aba0658ee9257387433d1699cfbc2e51e63</originalsourceid><addsrcrecordid>eNpFkMtqAkEQRTsPIaPJDySb-YGeVFW_l2JegpCFyVp6ZqqHFqMyI5H8fYQIWd0DFw6XK8Q9QoUI4XG-nE2XFQGEyiA6R3QhxqhJa-XJ60tREBov0ZC5-i-cvRYFkEOpFdBIFB6k1dYouBHjYVgDnIyWCuGfeMjdttylMpb73ZF7GY-x57LNXT7ETZm_Ysdlz2tuDnm3PVHD-Zv7WzFKcTPw3Tkn4vPl-WP2Jhfvr_PZdCEzYTjIFr21TidbJ5ecoVCb5BMYb2vLEOsI1njmQMYp77RSLdoQmlQ3xAbZqol4-PNmZl7t-9Oe_md1vkL9AuaXS08</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Design of a power-aware digital image rejection receiver</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Cetin, E. ; Kale, I. ; Morling, R.C.S.</creator><creatorcontrib>Cetin, E. ; Kale, I. ; Morling, R.C.S.</creatorcontrib><description>This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 1424438276</identifier><identifier>ISBN: 9781424438273</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 1424438284</identifier><identifier>EISBN: 9781424438280</identifier><identifier>DOI: 10.1109/ISCAS.2009.5117722</identifier><identifier>LCCN: 80-646530</identifier><language>eng</language><publisher>IEEE</publisher><subject>Baseband ; Degradation ; Digital images ; Digital signal processing ; Energy consumption ; Hydrogen ; Radio frequency ; RF signals ; Signal processing ; Very large scale integration</subject><ispartof>2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.209-212</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5117722$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5117722$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Cetin, E.</creatorcontrib><creatorcontrib>Kale, I.</creatorcontrib><creatorcontrib>Morling, R.C.S.</creatorcontrib><title>Design of a power-aware digital image rejection receiver</title><title>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.</description><subject>Baseband</subject><subject>Degradation</subject><subject>Digital images</subject><subject>Digital signal processing</subject><subject>Energy consumption</subject><subject>Hydrogen</subject><subject>Radio frequency</subject><subject>RF signals</subject><subject>Signal processing</subject><subject>Very large scale integration</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424438276</isbn><isbn>9781424438273</isbn><isbn>1424438284</isbn><isbn>9781424438280</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkMtqAkEQRTsPIaPJDySb-YGeVFW_l2JegpCFyVp6ZqqHFqMyI5H8fYQIWd0DFw6XK8Q9QoUI4XG-nE2XFQGEyiA6R3QhxqhJa-XJ60tREBov0ZC5-i-cvRYFkEOpFdBIFB6k1dYouBHjYVgDnIyWCuGfeMjdttylMpb73ZF7GY-x57LNXT7ETZm_Ysdlz2tuDnm3PVHD-Zv7WzFKcTPw3Tkn4vPl-WP2Jhfvr_PZdCEzYTjIFr21TidbJ5ecoVCb5BMYb2vLEOsI1njmQMYp77RSLdoQmlQ3xAbZqol4-PNmZl7t-9Oe_md1vkL9AuaXS08</recordid><startdate>20090101</startdate><enddate>20090101</enddate><creator>Cetin, E.</creator><creator>Kale, I.</creator><creator>Morling, R.C.S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>20090101</creationdate><title>Design of a power-aware digital image rejection receiver</title><author>Cetin, E. ; Kale, I. ; Morling, R.C.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i219t-d186674f6bf7f7529b5f8f0586b6e0aba0658ee9257387433d1699cfbc2e51e63</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Baseband</topic><topic>Degradation</topic><topic>Digital images</topic><topic>Digital signal processing</topic><topic>Energy consumption</topic><topic>Hydrogen</topic><topic>Radio frequency</topic><topic>RF signals</topic><topic>Signal processing</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Cetin, E.</creatorcontrib><creatorcontrib>Kale, I.</creatorcontrib><creatorcontrib>Morling, R.C.S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cetin, E.</au><au>Kale, I.</au><au>Morling, R.C.S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design of a power-aware digital image rejection receiver</atitle><btitle>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2009-01-01</date><risdate>2009</risdate><spage>209</spage><epage>212</epage><pages>209-212</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424438276</isbn><isbn>9781424438273</isbn><eisbn>1424438284</eisbn><eisbn>9781424438280</eisbn><abstract>This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2009.5117722</doi><tpages>4</tpages><oa>free_for_read</oa></addata></record> |
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identifier | ISSN: 0271-4302 |
ispartof | 2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.209-212 |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Baseband Degradation Digital images Digital signal processing Energy consumption Hydrogen Radio frequency RF signals Signal processing Very large scale integration |
title | Design of a power-aware digital image rejection receiver |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T09%3A39%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Design%20of%20a%20power-aware%20digital%20image%20rejection%20receiver&rft.btitle=2009%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Cetin,%20E.&rft.date=2009-01-01&rft.spage=209&rft.epage=212&rft.pages=209-212&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=1424438276&rft.isbn_list=9781424438273&rft_id=info:doi/10.1109/ISCAS.2009.5117722&rft_dat=%3Cieee_6IE%3E5117722%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424438284&rft.eisbn_list=9781424438280&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5117722&rfr_iscdi=true |