Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing
Two critical aspects of sense amplifiers (SA), power consumption and clock-to-data delay, are studied and presented for operation under low-supply voltage and driven by low-swing clock. Trade-offs and simulation results are given for a 4-stack StrongARM and a 3-stack double-tail SA, showing up to 50...
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| creator | Tao Jiang Chiang, P.Y. |
| description | Two critical aspects of sense amplifiers (SA), power consumption and clock-to-data delay, are studied and presented for operation under low-supply voltage and driven by low-swing clock. Trade-offs and simulation results are given for a 4-stack StrongARM and a 3-stack double-tail SA, showing up to 50% power reduction in the SA itself and 25% in the clock generation circuit, with acceptable delay degradation. |
| doi_str_mv | 10.1109/ISCAS.2009.5117715 |
| format | Conference Proceeding |
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Trade-offs and simulation results are given for a 4-stack StrongARM and a 3-stack double-tail SA, showing up to 50% power reduction in the SA itself and 25% in the clock generation circuit, with acceptable delay degradation.</description><subject>Circuit simulation</subject><subject>Clocks</subject><subject>Computer science</subject><subject>Degradation</subject><subject>Delay</subject><subject>Energy consumption</subject><subject>Low voltage</subject><subject>Operational amplifiers</subject><subject>Power supplies</subject><subject>Tail</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424438276</isbn><isbn>9781424438273</isbn><isbn>1424438284</isbn><isbn>9781424438280</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFUMtOwkAUHR8kFvQHdDM_ULzzbpeE-CAxcYG6JZeZWxgtbdNWCX69KCRu7jkn57G4jF0LGAsB-e1sPp3MxxIgHxshnBPmhA2FllqrTGb6lCVSmCwVRpqzf8PZc5aAdCLVCuSAJRmkVluj4IINu-4dYL9oZcLWc6o64rhpylhEanlTb_cXq8ADlbjjfo0t-p7a-I19rCte1C2vG2oP6rMK-3hZb9O3EP5qv_yrLntcEfdl7T94t43V6pINCiw7ujriiL3e371MH9On54fZdPKURuFMnxqQ1oMPeSEtofMOUOdIORZgM0nKQ24EWRP0EiXmqIP1Ymm1C1SoLFNqxG4Ou5GIFk0bN9juFsfXqR8FB15k</recordid><startdate>200905</startdate><enddate>200905</enddate><creator>Tao Jiang</creator><creator>Chiang, P.Y.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200905</creationdate><title>Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing</title><author>Tao Jiang ; Chiang, P.Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-5026c0cd9f26ea7c70a49ae9af0682e3c0951e65d4ba2a9a4d6c1b647def38833</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Circuit simulation</topic><topic>Clocks</topic><topic>Computer science</topic><topic>Degradation</topic><topic>Delay</topic><topic>Energy consumption</topic><topic>Low voltage</topic><topic>Operational amplifiers</topic><topic>Power supplies</topic><topic>Tail</topic><toplevel>online_resources</toplevel><creatorcontrib>Tao Jiang</creatorcontrib><creatorcontrib>Chiang, P.Y.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tao Jiang</au><au>Chiang, P.Y.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing</atitle><btitle>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2009-05</date><risdate>2009</risdate><spage>181</spage><epage>184</epage><pages>181-184</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424438276</isbn><isbn>9781424438273</isbn><eisbn>1424438284</eisbn><eisbn>9781424438280</eisbn><abstract>Two critical aspects of sense amplifiers (SA), power consumption and clock-to-data delay, are studied and presented for operation under low-supply voltage and driven by low-swing clock. Trade-offs and simulation results are given for a 4-stack StrongARM and a 3-stack double-tail SA, showing up to 50% power reduction in the SA itself and 25% in the clock generation circuit, with acceptable delay degradation.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2009.5117715</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 0271-4302 |
| ispartof | 2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.181-184 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_5117715 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit simulation Clocks Computer science Degradation Delay Energy consumption Low voltage Operational amplifiers Power supplies Tail |
| title | Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing |
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