Automated Debug of Speed Path Failures Using Functional Tests
Debug of at-speed failures using functional tests is a key challenge as part of frequency pushes during post-silicon debug to improve performance of high performance designs, especially microprocessors. In this paper, we present a technique to automate the debug of speed path failures using failing...
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| creator | McLaughlin, R. Venkataraman, S. Lim, C. |
| description | Debug of at-speed failures using functional tests is a key challenge as part of frequency pushes during post-silicon debug to improve performance of high performance designs, especially microprocessors. In this paper, we present a technique to automate the debug of speed path failures using failing functional tests by extracting information from design-for-debug features and then algorithmically isolating the internal speed-paths that could be the source of the failures. Results from application of the technique during silicon debug on the Intel reg Coretrade i7 quad-core processor is presented. |
| doi_str_mv | 10.1109/VTS.2009.53 |
| format | Conference Proceeding |
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Results from application of the technique during silicon debug on the Intel reg Coretrade i7 quad-core processor is presented.</description><subject>Algorithm design and analysis</subject><subject>Automatic testing</subject><subject>Circuit simulation</subject><subject>Computer bugs</subject><subject>Data mining</subject><subject>design for debug</subject><subject>Frequency</subject><subject>functional tests</subject><subject>Microprocessors</subject><subject>Silicon</subject><subject>Silicon debug</subject><subject>speed-path</subject><subject>System testing</subject><subject>Timing</subject><issn>1093-0167</issn><issn>2375-1053</issn><isbn>0769535984</isbn><isbn>9780769535982</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjM1Kw0AYRQd_wFi7culmXiDx--Y3s3BRaqNCQaGp2zJJZupImpRMsvDtDejdXA7ccwm5R8gQwTx-lruMAZhM8guSMK5liiD5JbkFrYzk0uTiiiTzlKeASt-QZYzfMIcbpXKRkKfVNPYnO7qGPrtqOtLe093Zzfhhxy9a2NBOg4t0H0N3pMXU1WPoO9vS0sUx3pFrb9volv-9IPtiU65f0-37y9t6tU0DEzimEhk3rPLecAtO1V6wXAGrlLa2gQakBdEYlte1R-YrobRoJGqLs2MEML4gD3-_wTl3OA_hZIefg0RUCiX_BQmSSAU</recordid><startdate>200905</startdate><enddate>200905</enddate><creator>McLaughlin, R.</creator><creator>Venkataraman, S.</creator><creator>Lim, C.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200905</creationdate><title>Automated Debug of Speed Path Failures Using Functional Tests</title><author>McLaughlin, R. ; Venkataraman, S. ; Lim, C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i241t-512392bff93a0e6cf428602b67aad0d05a04d928ccf12fb4674d517a12bf94023</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Algorithm design and analysis</topic><topic>Automatic testing</topic><topic>Circuit simulation</topic><topic>Computer bugs</topic><topic>Data mining</topic><topic>design for debug</topic><topic>Frequency</topic><topic>functional tests</topic><topic>Microprocessors</topic><topic>Silicon</topic><topic>Silicon debug</topic><topic>speed-path</topic><topic>System testing</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>McLaughlin, R.</creatorcontrib><creatorcontrib>Venkataraman, S.</creatorcontrib><creatorcontrib>Lim, C.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>McLaughlin, R.</au><au>Venkataraman, S.</au><au>Lim, C.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Automated Debug of Speed Path Failures Using Functional Tests</atitle><btitle>2009 27th IEEE VLSI Test Symposium</btitle><stitle>VTS</stitle><date>2009-05</date><risdate>2009</risdate><spage>91</spage><epage>96</epage><pages>91-96</pages><issn>1093-0167</issn><eissn>2375-1053</eissn><isbn>0769535984</isbn><isbn>9780769535982</isbn><abstract>Debug of at-speed failures using functional tests is a key challenge as part of frequency pushes during post-silicon debug to improve performance of high performance designs, especially microprocessors. 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| ispartof | 2009 27th IEEE VLSI Test Symposium, 2009, p.91-96 |
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| language | eng |
| recordid | cdi_ieee_primary_5116615 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Automatic testing Circuit simulation Computer bugs Data mining design for debug Frequency functional tests Microprocessors Silicon Silicon debug speed-path System testing Timing |
| title | Automated Debug of Speed Path Failures Using Functional Tests |
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