Serendipitous SEU hardening of resistive load SRAMs

Serendipitous SEU hardening of resistive load SRAMs

High and low resistive load versions of Micron Technology's MT5C1008C(128 K/spl times/8) and MT5C2561C(256 K/spl times/1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load A substantially larger number o...

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Bibliographische Detailangaben
Hauptverfasser: Koga, R., Kirshman, J.F., Pinkerton, S.D., Hansel, S.J., Crawford, K.B., Crain, W.R.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Aerospace testing
Circuits
CMOS technology
Computer errors
Computer simulation
MOSFETs
Particle beams
Random access memory
Single event upset
SRAM chips
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Zusammenfassung:High and low resistive load versions of Micron Technology's MT5C1008C(128 K/spl times/8) and MT5C2561C(256 K/spl times/1) SRAMs were tested for SEU vulnerability. Contrary to computer simulation results, SEU susceptibility decreased with increasing resistive load A substantially larger number of multiple-bit errors were observed for the low resistive load SRAMs, which also exhibited a "1"/spl rarr/"0" to "0"/spl rarr/"1" bit error ratio close to unity; in contrast, the high resistive load devices displayed a pronounced error bit polarity effect. Two distinct upset mechanisms are proposed to account for these observations.
DOI:10.1109/RADECS.1995.509802