Comparative study of the radiation hardness of an analog CMOS pipeline, discrete MOS transistors and interface traps in MOS capacitors

The ZEUS experiment at HERA employs a custom made analog pipeline, manufactured with a 2 /spl mu/m CMOS process. The standard transistor layout was not sufficiently radiation hard. After introducing thin oxide extension and guard bands, the pipeline worked after irradiation, up to 500 krad, with onl...

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Bibliographische Detailangaben

Hauptverfasser:	Bottcher, S., Coldewey, C., Croitoru, N., Seidman, A., Vogt, H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits CMOS process Degradation Density measurement Manufacturing processes MOS capacitors Photonic band gap Pipelines Silicon Threshold voltage
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