Increasing the accuracy of SAT-based debugging

Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. In particular, debugging based on Boolean satisfiability (SAT) has been shown to be quite efficient. Given some error trac...

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Bibliographische Detailangaben

Hauptverfasser:	Sulflow, A., Fey, G., Braunstein, C., Kuhne, U., Drechsler, R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analytical models Circuit faults Computer errors Computer Science Debugging Design automation Formal verification Manuals Process design Productivity
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