Board level temperature cycling study of large array Wafer Level Package

The demand for wafer level packages (WLP) has increased significantly due to its smaller package size and lower cost. However, board level reliability of WLP is still a major concern. This study investigates the board level temperature cycle reliability of three very different wafer level package co...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Rahim, M.S.K., Tiao Zhou, Xuejun Fan, Rupp, G.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Costs Failure analysis Fatigue Finite element methods Packaging Semiconductor device modeling Soldering Temperature Testing Wafer scale integration
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