Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links
To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-o...
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| creator | Bainbridge, W.J. Salisbury, S.J. |
| description | To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-on-chip (NoC) using quasi delay-insensitive (QDI) techniques. This is followed by the introduction and analysis of a set of techniques to reduce the likelihood and impact of such hazards affecting the circuit. Post layout area and performance impacts are presented for a 90 nm process. |
| doi_str_mv | 10.1109/ASYNC.2009.18 |
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| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5010334</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5010334</ieee_id><sourcerecordid>5010334</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-7fbad0fc34e6e631f155f0b75b640115274b469f9a071357338da5c23a0107763</originalsourceid><addsrcrecordid>eNotjkFLwzAYhgMqOOeOnrzkD6R-X9MkzXFUnYOyIdvF00jbhMXVdjRV6b83ME8vPO_Ly0PIA0KCCPppufvYFEkKoBPMr8hCqxyU1IJLlPyazFCkKctljrfkLoRPAFCIOCPbVevH-kh3tgt-9D9-nKjpGvpsXSSW9o6-f5vgI2jNxNaRXYaWbuz42w8n1nesOPozLX13Cvfkxpk22MV_zsn-9WVfvLFyu1oXy5J5DSNTrjINuJpnVlrJ0aEQDiolKpkBRleVVZnUTpuoyYXiPG-MqFNuAEEpyefk8XLrrbWH8-C_zDAdRGw5z_gfrMdMrA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Bainbridge, W.J. ; Salisbury, S.J.</creator><creatorcontrib>Bainbridge, W.J. ; Salisbury, S.J.</creatorcontrib><description>To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-on-chip (NoC) using quasi delay-insensitive (QDI) techniques. This is followed by the introduction and analysis of a set of techniques to reduce the likelihood and impact of such hazards affecting the circuit. Post layout area and performance impacts are presented for a 90 nm process.</description><identifier>ISSN: 1522-8681</identifier><identifier>ISBN: 9780769536163</identifier><identifier>ISBN: 9781424439331</identifier><identifier>ISBN: 1424439337</identifier><identifier>ISBN: 0769536166</identifier><identifier>DOI: 10.1109/ASYNC.2009.18</identifier><language>eng</language><publisher>IEEE</publisher><subject>Asynchronous ; Asynchronous circuits ; Delay effects ; Delay Insensitive ; Electromagnetic coupling ; Electromagnetic interference ; Glitch ; Hazard ; Hazards ; Integrated circuit interconnections ; Logic circuits ; Network-on-a-chip ; Network-on-Chip ; NoC ; Pipelines ; QDI ; Wires</subject><ispartof>2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009, p.35-44</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5010334$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5010334$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bainbridge, W.J.</creatorcontrib><creatorcontrib>Salisbury, S.J.</creatorcontrib><title>Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links</title><title>2009 15th IEEE Symposium on Asynchronous Circuits and Systems</title><addtitle>ASYNC</addtitle><description>To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-on-chip (NoC) using quasi delay-insensitive (QDI) techniques. This is followed by the introduction and analysis of a set of techniques to reduce the likelihood and impact of such hazards affecting the circuit. Post layout area and performance impacts are presented for a 90 nm process.</description><subject>Asynchronous</subject><subject>Asynchronous circuits</subject><subject>Delay effects</subject><subject>Delay Insensitive</subject><subject>Electromagnetic coupling</subject><subject>Electromagnetic interference</subject><subject>Glitch</subject><subject>Hazard</subject><subject>Hazards</subject><subject>Integrated circuit interconnections</subject><subject>Logic circuits</subject><subject>Network-on-a-chip</subject><subject>Network-on-Chip</subject><subject>NoC</subject><subject>Pipelines</subject><subject>QDI</subject><subject>Wires</subject><issn>1522-8681</issn><isbn>9780769536163</isbn><isbn>9781424439331</isbn><isbn>1424439337</isbn><isbn>0769536166</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjkFLwzAYhgMqOOeOnrzkD6R-X9MkzXFUnYOyIdvF00jbhMXVdjRV6b83ME8vPO_Ly0PIA0KCCPppufvYFEkKoBPMr8hCqxyU1IJLlPyazFCkKctljrfkLoRPAFCIOCPbVevH-kh3tgt-9D9-nKjpGvpsXSSW9o6-f5vgI2jNxNaRXYaWbuz42w8n1nesOPozLX13Cvfkxpk22MV_zsn-9WVfvLFyu1oXy5J5DSNTrjINuJpnVlrJ0aEQDiolKpkBRleVVZnUTpuoyYXiPG-MqFNuAEEpyefk8XLrrbWH8-C_zDAdRGw5z_gfrMdMrA</recordid><startdate>200905</startdate><enddate>200905</enddate><creator>Bainbridge, W.J.</creator><creator>Salisbury, S.J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200905</creationdate><title>Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links</title><author>Bainbridge, W.J. ; Salisbury, S.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-7fbad0fc34e6e631f155f0b75b640115274b469f9a071357338da5c23a0107763</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Asynchronous</topic><topic>Asynchronous circuits</topic><topic>Delay effects</topic><topic>Delay Insensitive</topic><topic>Electromagnetic coupling</topic><topic>Electromagnetic interference</topic><topic>Glitch</topic><topic>Hazard</topic><topic>Hazards</topic><topic>Integrated circuit interconnections</topic><topic>Logic circuits</topic><topic>Network-on-a-chip</topic><topic>Network-on-Chip</topic><topic>NoC</topic><topic>Pipelines</topic><topic>QDI</topic><topic>Wires</topic><toplevel>online_resources</toplevel><creatorcontrib>Bainbridge, W.J.</creatorcontrib><creatorcontrib>Salisbury, S.J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bainbridge, W.J.</au><au>Salisbury, S.J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links</atitle><btitle>2009 15th IEEE Symposium on Asynchronous Circuits and Systems</btitle><stitle>ASYNC</stitle><date>2009-05</date><risdate>2009</risdate><spage>35</spage><epage>44</epage><pages>35-44</pages><issn>1522-8681</issn><isbn>9780769536163</isbn><isbn>9781424439331</isbn><isbn>1424439337</isbn><isbn>0769536166</isbn><abstract>To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-on-chip (NoC) using quasi delay-insensitive (QDI) techniques. This is followed by the introduction and analysis of a set of techniques to reduce the likelihood and impact of such hazards affecting the circuit. Post layout area and performance impacts are presented for a 90 nm process.</abstract><pub>IEEE</pub><doi>10.1109/ASYNC.2009.18</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 1522-8681 |
| ispartof | 2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009, p.35-44 |
| issn | 1522-8681 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Asynchronous Asynchronous circuits Delay effects Delay Insensitive Electromagnetic coupling Electromagnetic interference Glitch Hazard Hazards Integrated circuit interconnections Logic circuits Network-on-a-chip Network-on-Chip NoC Pipelines QDI Wires |
| title | Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T01%3A20%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Glitch%20Sensitivity%20and%20Defense%20of%20Quasi%20Delay-Insensitive%20Network-on-Chip%20Links&rft.btitle=2009%2015th%20IEEE%20Symposium%20on%20Asynchronous%20Circuits%20and%20Systems&rft.au=Bainbridge,%20W.J.&rft.date=2009-05&rft.spage=35&rft.epage=44&rft.pages=35-44&rft.issn=1522-8681&rft.isbn=9780769536163&rft.isbn_list=9781424439331&rft.isbn_list=1424439337&rft.isbn_list=0769536166&rft_id=info:doi/10.1109/ASYNC.2009.18&rft_dat=%3Cieee_6IE%3E5010334%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5010334&rfr_iscdi=true |