A 40Gb/s full-rate 2:1 MUX in 0.18µm CMOS
Serial data communication systems operating at throughputs of 40 Gb/s have been developed in recent years to increase transmission capacity. A data multiplexer (MUX) is a key block in any high-speed data communication system. Several 4:1 MUX circuits have been reported in technologies such as SiGe,...
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| creator | Yazdi, A. Green, M.M. |
| description | Serial data communication systems operating at throughputs of 40 Gb/s have been developed in recent years to increase transmission capacity. A data multiplexer (MUX) is a key block in any high-speed data communication system. Several 4:1 MUX circuits have been reported in technologies such as SiGe, GaAsand InP at speeds of 40 Gb/s or higher. CMOS implementations of half-rate MUX circuits have been also reported. A full-rate architecture would be desirable in order to reduce the deterministic jitter. This paper describes high-speed design techniques used for retiming of 40 Gb/s data signals and generation of 40 GHz clock signals. |
| doi_str_mv | 10.1109/ISSCC.2009.4977458 |
| format | Conference Proceeding |
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A data multiplexer (MUX) is a key block in any high-speed data communication system. Several 4:1 MUX circuits have been reported in technologies such as SiGe, GaAsand InP at speeds of 40 Gb/s or higher. CMOS implementations of half-rate MUX circuits have been also reported. A full-rate architecture would be desirable in order to reduce the deterministic jitter. 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A data multiplexer (MUX) is a key block in any high-speed data communication system. Several 4:1 MUX circuits have been reported in technologies such as SiGe, GaAsand InP at speeds of 40 Gb/s or higher. CMOS implementations of half-rate MUX circuits have been also reported. A full-rate architecture would be desirable in order to reduce the deterministic jitter. This paper describes high-speed design techniques used for retiming of 40 Gb/s data signals and generation of 40 GHz clock signals.</description><subject>Circuits</subject><subject>CMOS technology</subject><subject>Data communication</subject><subject>Germanium silicon alloys</subject><subject>Indium phosphide</subject><subject>Jitter</subject><subject>Multiplexing</subject><subject>Signal design</subject><subject>Silicon germanium</subject><subject>Throughput</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>9781424434589</isbn><isbn>1424434580</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9zj0OgkAUBOAXlUSiXECbrU0W3rKPZdfOEP8KYoEmdgSTJcGAMaCFB_MCnkwKa6eZ4itmAGYCfSHQBPssSxI_RDQ-mTimSA_ADWWsuFaohuCZWAsKiWRPZgQuCiO5iiQ64GrBFZEWOAav667Yh3rR5MJixQi3l6Bj5bOueVs8LAuXgqWnM6turF_Xn3fDkvSQTcEpi7qz3q8nMN-sj8mOV9ba_N5WTdG-8t87-V-_jmg0Cg</recordid><startdate>200902</startdate><enddate>200902</enddate><creator>Yazdi, A.</creator><creator>Green, M.M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200902</creationdate><title>A 40Gb/s full-rate 2:1 MUX in 0.18µm CMOS</title><author>Yazdi, A. ; Green, M.M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_49774583</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Circuits</topic><topic>CMOS technology</topic><topic>Data communication</topic><topic>Germanium silicon alloys</topic><topic>Indium phosphide</topic><topic>Jitter</topic><topic>Multiplexing</topic><topic>Signal design</topic><topic>Silicon germanium</topic><topic>Throughput</topic><toplevel>online_resources</toplevel><creatorcontrib>Yazdi, A.</creatorcontrib><creatorcontrib>Green, M.M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yazdi, A.</au><au>Green, M.M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 40Gb/s full-rate 2:1 MUX in 0.18µm CMOS</atitle><btitle>2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers</btitle><stitle>ISSCC</stitle><date>2009-02</date><risdate>2009</risdate><spage>362</spage><epage>363,363a</epage><pages>362-363,363a</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>9781424434589</isbn><isbn>1424434580</isbn><abstract>Serial data communication systems operating at throughputs of 40 Gb/s have been developed in recent years to increase transmission capacity. A data multiplexer (MUX) is a key block in any high-speed data communication system. Several 4:1 MUX circuits have been reported in technologies such as SiGe, GaAsand InP at speeds of 40 Gb/s or higher. CMOS implementations of half-rate MUX circuits have been also reported. A full-rate architecture would be desirable in order to reduce the deterministic jitter. This paper describes high-speed design techniques used for retiming of 40 Gb/s data signals and generation of 40 GHz clock signals.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2009.4977458</doi></addata></record> |
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| ispartof | 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.362-363,363a |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_4977458 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits CMOS technology Data communication Germanium silicon alloys Indium phosphide Jitter Multiplexing Signal design Silicon germanium Throughput |
| title | A 40Gb/s full-rate 2:1 MUX in 0.18µm CMOS |
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