Limitation of the signal pin density on wiring boards
A practical limit of the signal pin density on wiring boards is investigated from the wireability point of view. The wireability problem can be expressed as a supply and demand model of two resources, i.e. wiring channels and via-holes. The limit of the signal pin density is assumed to be determined...
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| Veröffentlicht in: | IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging packaging, and manufacturing technology. Part B, Advanced packaging, 1996-05, Vol.19 (2), p.391-396 |
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| container_end_page | 396 |
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| container_issue | 2 |
| container_start_page | 391 |
| container_title | IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging |
| container_volume | 19 |
| creator | Chiba, T. Yamada, M. Kobayashi, F. |
| description | A practical limit of the signal pin density on wiring boards is investigated from the wireability point of view. The wireability problem can be expressed as a supply and demand model of two resources, i.e. wiring channels and via-holes. The limit of the signal pin density is assumed to be determined by the shortage of either of these two resources. As a measure of pin density, the average distance between adjacent signal pins, s/sub T/, is introduced. The practical limit of s/sub T/ is estimated by analyzing the actual product data and experimental data. The lower bound of s/sub T/, normalized by the grid spacing, can range from 1.5 to 2.0. These results are applied as a guideline to estimate the footprint area per LSI, and to do design tradeoffs among different packaging technologies such as multichip modules (MCM). |
| doi_str_mv | 10.1109/96.496043 |
| format | Article |
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The wireability problem can be expressed as a supply and demand model of two resources, i.e. wiring channels and via-holes. The limit of the signal pin density is assumed to be determined by the shortage of either of these two resources. As a measure of pin density, the average distance between adjacent signal pins, s/sub T/, is introduced. The practical limit of s/sub T/ is estimated by analyzing the actual product data and experimental data. The lower bound of s/sub T/, normalized by the grid spacing, can range from 1.5 to 2.0. These results are applied as a guideline to estimate the footprint area per LSI, and to do design tradeoffs among different packaging technologies such as multichip modules (MCM).</description><identifier>ISSN: 1070-9894</identifier><identifier>EISSN: 1558-3686</identifier><identifier>DOI: 10.1109/96.496043</identifier><identifier>CODEN: IMTBE4</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Costs ; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics ; Electronics ; Exact sciences and technology ; Guidelines ; Large scale integration ; Multichip modules ; Packaging ; Pins ; Signal design ; Signal processing ; Space technology ; Wiring</subject><ispartof>IEEE transactions on components, packaging, and manufacturing technology. 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Part B, Advanced packaging</title><addtitle>T-CPMB</addtitle><description>A practical limit of the signal pin density on wiring boards is investigated from the wireability point of view. The wireability problem can be expressed as a supply and demand model of two resources, i.e. wiring channels and via-holes. The limit of the signal pin density is assumed to be determined by the shortage of either of these two resources. As a measure of pin density, the average distance between adjacent signal pins, s/sub T/, is introduced. The practical limit of s/sub T/ is estimated by analyzing the actual product data and experimental data. The lower bound of s/sub T/, normalized by the grid spacing, can range from 1.5 to 2.0. These results are applied as a guideline to estimate the footprint area per LSI, and to do design tradeoffs among different packaging technologies such as multichip modules (MCM).</description><subject>Applied sciences</subject><subject>Costs</subject><subject>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Guidelines</subject><subject>Large scale integration</subject><subject>Multichip modules</subject><subject>Packaging</subject><subject>Pins</subject><subject>Signal design</subject><subject>Signal processing</subject><subject>Space technology</subject><subject>Wiring</subject><issn>1070-9894</issn><issn>1558-3686</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1996</creationdate><recordtype>article</recordtype><recordid>eNo9j81LxDAQxYMouK4evHrKwYuHrpPmo8lRFr-g4EXPZZoma6TblqQg-98b6bJzmYH3mzfzCLllsGEMzKNRG2EUCH5GVkxKXXCl1XmeoYLCaCMuyVVKPwDAJWcrIuuwDzPOYRzo6On87WgKuwF7OoWBdm5IYT7QLP6GGIYdbUeMXbomFx775G6OfU2-Xp4_t29F_fH6vn2qC1tWci6EhnxeetCGGRAtL5VEa7vKc83zd9iiZYorYQ1nVatL71QpM4O-Y6AcX5OHxdfGMaXofDPFsMd4aBg0_3kbo5olb2bvF3bCZLH3EQcb0mmBs1xGZuxuwYJz7qQePf4AaxJbEw</recordid><startdate>19960501</startdate><enddate>19960501</enddate><creator>Chiba, T.</creator><creator>Yamada, M.</creator><creator>Kobayashi, F.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>19960501</creationdate><title>Limitation of the signal pin density on wiring boards</title><author>Chiba, T. ; Yamada, M. ; Kobayashi, F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c275t-4803685f0891904b3265accd7f383155abac16364c9317b82fe62565aafd106e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Applied sciences</topic><topic>Costs</topic><topic>Electronic equipment and fabrication. Passive components, printed wiring boards, connectics</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Guidelines</topic><topic>Large scale integration</topic><topic>Multichip modules</topic><topic>Packaging</topic><topic>Pins</topic><topic>Signal design</topic><topic>Signal processing</topic><topic>Space technology</topic><topic>Wiring</topic><toplevel>online_resources</toplevel><creatorcontrib>Chiba, T.</creatorcontrib><creatorcontrib>Yamada, M.</creatorcontrib><creatorcontrib>Kobayashi, F.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><jtitle>IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chiba, T.</au><au>Yamada, M.</au><au>Kobayashi, F.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Limitation of the signal pin density on wiring boards</atitle><jtitle>IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging</jtitle><stitle>T-CPMB</stitle><date>1996-05-01</date><risdate>1996</risdate><volume>19</volume><issue>2</issue><spage>391</spage><epage>396</epage><pages>391-396</pages><issn>1070-9894</issn><eissn>1558-3686</eissn><coden>IMTBE4</coden><abstract>A practical limit of the signal pin density on wiring boards is investigated from the wireability point of view. The wireability problem can be expressed as a supply and demand model of two resources, i.e. wiring channels and via-holes. The limit of the signal pin density is assumed to be determined by the shortage of either of these two resources. As a measure of pin density, the average distance between adjacent signal pins, s/sub T/, is introduced. The practical limit of s/sub T/ is estimated by analyzing the actual product data and experimental data. The lower bound of s/sub T/, normalized by the grid spacing, can range from 1.5 to 2.0. These results are applied as a guideline to estimate the footprint area per LSI, and to do design tradeoffs among different packaging technologies such as multichip modules (MCM).</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/96.496043</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 1070-9894 |
| ispartof | IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 1996-05, Vol.19 (2), p.391-396 |
| issn | 1070-9894 1558-3686 |
| language | eng |
| recordid | cdi_ieee_primary_496043 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Costs Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Guidelines Large scale integration Multichip modules Packaging Pins Signal design Signal processing Space technology Wiring |
| title | Limitation of the signal pin density on wiring boards |
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