Power, delay and area efficient self-timed multiplexer and demultiplexer designs
Efficient gate level design methods for robust self-timed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed in this paper. While the optimal self-timed multiplexer implementations correspond to strong-indic...
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| creator | Balasubramanian, P. Edwards, D.A. |
| description | Efficient gate level design methods for robust self-timed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed in this paper. While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. The design methods presented are scalable and enable achieving simultaneous optimization in power, delay and area parameters. |
| doi_str_mv | 10.1109/DTIS.2009.4938050 |
| format | Conference Proceeding |
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While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. 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While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. The design methods presented are scalable and enable achieving simultaneous optimization in power, delay and area parameters.</description><subject>Circuits</subject><subject>Delay</subject><subject>Design methodology</subject><subject>Encoding</subject><subject>Logic design</subject><subject>Multiplexing</subject><subject>Protocols</subject><subject>Robustness</subject><subject>Switches</subject><subject>Wires</subject><isbn>9781424443208</isbn><isbn>1424443202</isbn><isbn>9781424443215</isbn><isbn>1424443210</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtOwzAURI1QJaDkAxCbfAAJ16_YXqLyqlSJSpR1dWtfI6MkVHEQ9O95dQGzGc3oaBbD2BmHmnNwl9er-WMtAFytnLSg4YAVzliuhFJKCq4P_2WwE3byjTsQUuojVuT8Al9SWjihjtly-fpOw0UZqMVdiX0ocSAsKcbkE_VjmamN1Zg6CmX31o5p29IHDT9koL9NoJye-3zKJhHbTMXep-zp9mY1u68WD3fz2dWiSsKqsUJNXgjuDUY0Vm4omsCNByu4UZ5b6blGg6oRvsENaA0mGt3ERjhrPRo5Zee_u4mI1tshdTjs1vtT5Ceu01MH</recordid><startdate>200904</startdate><enddate>200904</enddate><creator>Balasubramanian, P.</creator><creator>Edwards, D.A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200904</creationdate><title>Power, delay and area efficient self-timed multiplexer and demultiplexer designs</title><author>Balasubramanian, P. ; Edwards, D.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i284t-a5ec221c7afa783bef7d17c082174c183c15a7a462c6ab05507f756f62988ca73</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Circuits</topic><topic>Delay</topic><topic>Design methodology</topic><topic>Encoding</topic><topic>Logic design</topic><topic>Multiplexing</topic><topic>Protocols</topic><topic>Robustness</topic><topic>Switches</topic><topic>Wires</topic><toplevel>online_resources</toplevel><creatorcontrib>Balasubramanian, P.</creatorcontrib><creatorcontrib>Edwards, D.A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Balasubramanian, P.</au><au>Edwards, D.A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Power, delay and area efficient self-timed multiplexer and demultiplexer designs</atitle><btitle>2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era</btitle><stitle>DTIS</stitle><date>2009-04</date><risdate>2009</risdate><spage>173</spage><epage>178</epage><pages>173-178</pages><isbn>9781424443208</isbn><isbn>1424443202</isbn><eisbn>9781424443215</eisbn><eisbn>1424443210</eisbn><abstract>Efficient gate level design methods for robust self-timed realization of arbitrary size multiplexer and demultiplexer function blocks, using elements of a commercial standard cell library are discussed in this paper. While the optimal self-timed multiplexer implementations correspond to strong-indication, the optimal self-timed demultiplexer implementations pertain to weak-indication phenomenon. The design methods presented are scalable and enable achieving simultaneous optimization in power, delay and area parameters.</abstract><pub>IEEE</pub><doi>10.1109/DTIS.2009.4938050</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Delay Design methodology Encoding Logic design Multiplexing Protocols Robustness Switches Wires |
| title | Power, delay and area efficient self-timed multiplexer and demultiplexer designs |
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