Dynamic compact model of Spin-Transfer Torque based Magnetic Tunnel Junction (MTJ)
The integration of magnetic tunnel junctions (MTJ) above CMOS circuits in embedded magnetic RAM (MRAM) or magnetic FPGA (MFPGA) could bring to digital circuits major advantages associated to non-volatile capability such as instant on/off, multi-context FPGA and zero standby power consumption. A comp...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 135 |
|---|---|
| container_issue | |
| container_start_page | 130 |
| container_title | |
| container_volume | |
| creator | Faber, L.-B. Weisheng Zhao Klein, J.-O. Devolder, T. Chappert, C. |
| description | The integration of magnetic tunnel junctions (MTJ) above CMOS circuits in embedded magnetic RAM (MRAM) or magnetic FPGA (MFPGA) could bring to digital circuits major advantages associated to non-volatile capability such as instant on/off, multi-context FPGA and zero standby power consumption. A complete simulation model for the hybrid MTJ/CMOS design is presented in this paper. Based on the recently demonstrated spin-transfer torque (STT) writing approach which promises to lower the switching current down to ~120 uA, we have added to the previous static model the dynamic behaviors as well as the switching probability and the thermal effects. The model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform. Many experimental parameters are included in this model to improve the simulation accuracy. Simulations demonstrate that the model can be efficiently used to design hybrid MTJ/CMOS circuits. |
| doi_str_mv | 10.1109/DTIS.2009.4938040 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4938040</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4938040</ieee_id><sourcerecordid>4938040</sourcerecordid><originalsourceid>FETCH-LOGICAL-c289t-d32e5bb964a9ac4a727520cf8455f2484b49f21cfc0d2c2b4d31e6937b9068ce3</originalsourceid><addsrcrecordid>eNpVkD1PwzAYhI1QJaDkByAWjzAk2K9fJ_aIWj5atUKiYa4cx0ZBjRPyMfTfE0QXbjmd9NwNR8gNZwnnTD8s89UuAcZ0gloohuyMRDpTHAERBXB5_i8zNSNXv7hmIIS8IFHff7FJKEEDXpL35TGYurLUNnVr7EDrpnQH2ni6a6sQ550JvXcdzZvue3S0ML0r6dZ8BjdMpXwMYaLXY7BD1QR6t83X99dk5s2hd9HJ5-Tj-SlfvMabt5fV4nETW1B6iEsBThaFTtFoY9FkkElg1iuU0gMqLFB74NZbVoKFAkvBXapFVmiWKuvEnNz-7VbOuX3bVbXpjvvTLeIHsj1SkA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Dynamic compact model of Spin-Transfer Torque based Magnetic Tunnel Junction (MTJ)</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Faber, L.-B. ; Weisheng Zhao ; Klein, J.-O. ; Devolder, T. ; Chappert, C.</creator><creatorcontrib>Faber, L.-B. ; Weisheng Zhao ; Klein, J.-O. ; Devolder, T. ; Chappert, C.</creatorcontrib><description>The integration of magnetic tunnel junctions (MTJ) above CMOS circuits in embedded magnetic RAM (MRAM) or magnetic FPGA (MFPGA) could bring to digital circuits major advantages associated to non-volatile capability such as instant on/off, multi-context FPGA and zero standby power consumption. A complete simulation model for the hybrid MTJ/CMOS design is presented in this paper. Based on the recently demonstrated spin-transfer torque (STT) writing approach which promises to lower the switching current down to ~120 uA, we have added to the previous static model the dynamic behaviors as well as the switching probability and the thermal effects. The model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform. Many experimental parameters are included in this model to improve the simulation accuracy. Simulations demonstrate that the model can be efficiently used to design hybrid MTJ/CMOS circuits.</description><identifier>ISBN: 9781424443208</identifier><identifier>ISBN: 1424443202</identifier><identifier>EISBN: 9781424443215</identifier><identifier>EISBN: 1424443210</identifier><identifier>DOI: 10.1109/DTIS.2009.4938040</identifier><identifier>LCCN: 2009902335</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; CMOS digital integrated circuits ; Digital circuits ; dynamic and static behavoirs ; Energy consumption ; Field programmable gate arrays ; high speed ; low power ; Magnetic circuits ; Magnetic tunneling ; MRAM ; MTJ ; Semiconductor device modeling ; STT ; thermal effects ; Torque ; Writing</subject><ispartof>2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, 2009, p.130-135</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c289t-d32e5bb964a9ac4a727520cf8455f2484b49f21cfc0d2c2b4d31e6937b9068ce3</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4938040$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4938040$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Faber, L.-B.</creatorcontrib><creatorcontrib>Weisheng Zhao</creatorcontrib><creatorcontrib>Klein, J.-O.</creatorcontrib><creatorcontrib>Devolder, T.</creatorcontrib><creatorcontrib>Chappert, C.</creatorcontrib><title>Dynamic compact model of Spin-Transfer Torque based Magnetic Tunnel Junction (MTJ)</title><title>2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era</title><addtitle>DTIS</addtitle><description>The integration of magnetic tunnel junctions (MTJ) above CMOS circuits in embedded magnetic RAM (MRAM) or magnetic FPGA (MFPGA) could bring to digital circuits major advantages associated to non-volatile capability such as instant on/off, multi-context FPGA and zero standby power consumption. A complete simulation model for the hybrid MTJ/CMOS design is presented in this paper. Based on the recently demonstrated spin-transfer torque (STT) writing approach which promises to lower the switching current down to ~120 uA, we have added to the previous static model the dynamic behaviors as well as the switching probability and the thermal effects. The model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform. Many experimental parameters are included in this model to improve the simulation accuracy. Simulations demonstrate that the model can be efficiently used to design hybrid MTJ/CMOS circuits.</description><subject>Circuit simulation</subject><subject>CMOS digital integrated circuits</subject><subject>Digital circuits</subject><subject>dynamic and static behavoirs</subject><subject>Energy consumption</subject><subject>Field programmable gate arrays</subject><subject>high speed</subject><subject>low power</subject><subject>Magnetic circuits</subject><subject>Magnetic tunneling</subject><subject>MRAM</subject><subject>MTJ</subject><subject>Semiconductor device modeling</subject><subject>STT</subject><subject>thermal effects</subject><subject>Torque</subject><subject>Writing</subject><isbn>9781424443208</isbn><isbn>1424443202</isbn><isbn>9781424443215</isbn><isbn>1424443210</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkD1PwzAYhI1QJaDkByAWjzAk2K9fJ_aIWj5atUKiYa4cx0ZBjRPyMfTfE0QXbjmd9NwNR8gNZwnnTD8s89UuAcZ0gloohuyMRDpTHAERBXB5_i8zNSNXv7hmIIS8IFHff7FJKEEDXpL35TGYurLUNnVr7EDrpnQH2ni6a6sQ550JvXcdzZvue3S0ML0r6dZ8BjdMpXwMYaLXY7BD1QR6t83X99dk5s2hd9HJ5-Tj-SlfvMabt5fV4nETW1B6iEsBThaFTtFoY9FkkElg1iuU0gMqLFB74NZbVoKFAkvBXapFVmiWKuvEnNz-7VbOuX3bVbXpjvvTLeIHsj1SkA</recordid><startdate>200904</startdate><enddate>200904</enddate><creator>Faber, L.-B.</creator><creator>Weisheng Zhao</creator><creator>Klein, J.-O.</creator><creator>Devolder, T.</creator><creator>Chappert, C.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200904</creationdate><title>Dynamic compact model of Spin-Transfer Torque based Magnetic Tunnel Junction (MTJ)</title><author>Faber, L.-B. ; Weisheng Zhao ; Klein, J.-O. ; Devolder, T. ; Chappert, C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c289t-d32e5bb964a9ac4a727520cf8455f2484b49f21cfc0d2c2b4d31e6937b9068ce3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Circuit simulation</topic><topic>CMOS digital integrated circuits</topic><topic>Digital circuits</topic><topic>dynamic and static behavoirs</topic><topic>Energy consumption</topic><topic>Field programmable gate arrays</topic><topic>high speed</topic><topic>low power</topic><topic>Magnetic circuits</topic><topic>Magnetic tunneling</topic><topic>MRAM</topic><topic>MTJ</topic><topic>Semiconductor device modeling</topic><topic>STT</topic><topic>thermal effects</topic><topic>Torque</topic><topic>Writing</topic><toplevel>online_resources</toplevel><creatorcontrib>Faber, L.-B.</creatorcontrib><creatorcontrib>Weisheng Zhao</creatorcontrib><creatorcontrib>Klein, J.-O.</creatorcontrib><creatorcontrib>Devolder, T.</creatorcontrib><creatorcontrib>Chappert, C.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Faber, L.-B.</au><au>Weisheng Zhao</au><au>Klein, J.-O.</au><au>Devolder, T.</au><au>Chappert, C.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Dynamic compact model of Spin-Transfer Torque based Magnetic Tunnel Junction (MTJ)</atitle><btitle>2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era</btitle><stitle>DTIS</stitle><date>2009-04</date><risdate>2009</risdate><spage>130</spage><epage>135</epage><pages>130-135</pages><isbn>9781424443208</isbn><isbn>1424443202</isbn><eisbn>9781424443215</eisbn><eisbn>1424443210</eisbn><abstract>The integration of magnetic tunnel junctions (MTJ) above CMOS circuits in embedded magnetic RAM (MRAM) or magnetic FPGA (MFPGA) could bring to digital circuits major advantages associated to non-volatile capability such as instant on/off, multi-context FPGA and zero standby power consumption. A complete simulation model for the hybrid MTJ/CMOS design is presented in this paper. Based on the recently demonstrated spin-transfer torque (STT) writing approach which promises to lower the switching current down to ~120 uA, we have added to the previous static model the dynamic behaviors as well as the switching probability and the thermal effects. The model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform. Many experimental parameters are included in this model to improve the simulation accuracy. Simulations demonstrate that the model can be efficiently used to design hybrid MTJ/CMOS circuits.</abstract><pub>IEEE</pub><doi>10.1109/DTIS.2009.4938040</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9781424443208 |
| ispartof | 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, 2009, p.130-135 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_4938040 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit simulation CMOS digital integrated circuits Digital circuits dynamic and static behavoirs Energy consumption Field programmable gate arrays high speed low power Magnetic circuits Magnetic tunneling MRAM MTJ Semiconductor device modeling STT thermal effects Torque Writing |
| title | Dynamic compact model of Spin-Transfer Torque based Magnetic Tunnel Junction (MTJ) |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T04%3A05%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Dynamic%20compact%20model%20of%20Spin-Transfer%20Torque%20based%20Magnetic%20Tunnel%20Junction%20(MTJ)&rft.btitle=2009%204th%20International%20Conference%20on%20Design%20&%20Technology%20of%20Integrated%20Systems%20in%20Nanoscal%20Era&rft.au=Faber,%20L.-B.&rft.date=2009-04&rft.spage=130&rft.epage=135&rft.pages=130-135&rft.isbn=9781424443208&rft.isbn_list=1424443202&rft_id=info:doi/10.1109/DTIS.2009.4938040&rft_dat=%3Cieee_6IE%3E4938040%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424443215&rft.eisbn_list=1424443210&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4938040&rfr_iscdi=true |