Concurrent calculations on reconfigurable logic devices applied to the analisys of video images
This paper presents the design and implementation on FPGA devices of an algorithm for computing the similarity between neighbor photograms in a video sequence using luminance information. Making use of the well-known flexibility of reconfigurable logic devices, we have designed a hardware implementa...
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creator | Geninatti, Sergio R. Calvino, Manuel Hernandez Benitez, Jose Ignacio Benavides Mata, Nicolas Guil |
description | This paper presents the design and implementation on FPGA devices of an algorithm for computing the similarity between neighbor photograms in a video sequence using luminance information. Making use of the well-known flexibility of reconfigurable logic devices, we have designed a hardware implementation of the algorithm used in video segmentation and indexation. The experimental work has established a tradeoff between concurrent sequential resources and functional blocks, in order to achieve maximum operation speed with minimum silicon area. In order to evaluate the efficiency of the designed system, we have compared the performance of the hardware solution with that of calculations done via software using general-purpose processors with and without the MMX extension. |
doi_str_mv | 10.1109/SPL.2009.4914889 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4914889</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4914889</ieee_id><sourcerecordid>4914889</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-a538fbff62a29e687f466dc726e38db41d843f9908ac93e21c122ada361e88eb3</originalsourceid><addsrcrecordid>eNotUEtLAzEYDEhBW3sXvOQPtObV3eQoxRcsKKjn5dvkS43EzZLsFvrvXbFzmcMwM8wQcsPZlnNm7t7fmq1gzGyV4Uprc0GWXAmlpFY1W5Dln2YYU4ZdknUp32yG2gnDxBVp96m3U87Yj9RCtFOEMaS-0NTTjDb1PhymDF1EGtMhWOrwGCwWCsMQAzo6Jjp-IYUeYiin2efpMThMNPzAAcs1WXiIBddnXpHPx4eP_fOmeX162d83m8Dr3biBndS-874SIAxWuvaqqpytRYVSu05xp5X08woN1kgU3HIhwIGsOGqNnVyR2__cgIjtkOf2fGrPh8hfp0BV3A</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Concurrent calculations on reconfigurable logic devices applied to the analisys of video images</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Geninatti, Sergio R. ; Calvino, Manuel Hernandez ; Benitez, Jose Ignacio Benavides ; Mata, Nicolas Guil</creator><creatorcontrib>Geninatti, Sergio R. ; Calvino, Manuel Hernandez ; Benitez, Jose Ignacio Benavides ; Mata, Nicolas Guil</creatorcontrib><description>This paper presents the design and implementation on FPGA devices of an algorithm for computing the similarity between neighbor photograms in a video sequence using luminance information. Making use of the well-known flexibility of reconfigurable logic devices, we have designed a hardware implementation of the algorithm used in video segmentation and indexation. The experimental work has established a tradeoff between concurrent sequential resources and functional blocks, in order to achieve maximum operation speed with minimum silicon area. In order to evaluate the efficiency of the designed system, we have compared the performance of the hardware solution with that of calculations done via software using general-purpose processors with and without the MMX extension.</description><identifier>ISBN: 1424438470</identifier><identifier>ISBN: 9781424438471</identifier><identifier>DOI: 10.1109/SPL.2009.4914889</identifier><identifier>LCCN: 2009900490</identifier><language>eng</language><publisher>IEEE</publisher><subject>Algorithm design and analysis ; Circuits ; Clocks ; Concurrent computing ; Field programmable gate arrays ; Frequency ; Hardware ; Humans ; Logic devices ; Reconfigurable logic</subject><ispartof>2009 5th Southern Conference on Programmable Logic (SPL), 2009, p.109-114</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4914889$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4914889$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Geninatti, Sergio R.</creatorcontrib><creatorcontrib>Calvino, Manuel Hernandez</creatorcontrib><creatorcontrib>Benitez, Jose Ignacio Benavides</creatorcontrib><creatorcontrib>Mata, Nicolas Guil</creatorcontrib><title>Concurrent calculations on reconfigurable logic devices applied to the analisys of video images</title><title>2009 5th Southern Conference on Programmable Logic (SPL)</title><addtitle>SPL</addtitle><description>This paper presents the design and implementation on FPGA devices of an algorithm for computing the similarity between neighbor photograms in a video sequence using luminance information. Making use of the well-known flexibility of reconfigurable logic devices, we have designed a hardware implementation of the algorithm used in video segmentation and indexation. The experimental work has established a tradeoff between concurrent sequential resources and functional blocks, in order to achieve maximum operation speed with minimum silicon area. In order to evaluate the efficiency of the designed system, we have compared the performance of the hardware solution with that of calculations done via software using general-purpose processors with and without the MMX extension.</description><subject>Algorithm design and analysis</subject><subject>Circuits</subject><subject>Clocks</subject><subject>Concurrent computing</subject><subject>Field programmable gate arrays</subject><subject>Frequency</subject><subject>Hardware</subject><subject>Humans</subject><subject>Logic devices</subject><subject>Reconfigurable logic</subject><isbn>1424438470</isbn><isbn>9781424438471</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotUEtLAzEYDEhBW3sXvOQPtObV3eQoxRcsKKjn5dvkS43EzZLsFvrvXbFzmcMwM8wQcsPZlnNm7t7fmq1gzGyV4Uprc0GWXAmlpFY1W5Dln2YYU4ZdknUp32yG2gnDxBVp96m3U87Yj9RCtFOEMaS-0NTTjDb1PhymDF1EGtMhWOrwGCwWCsMQAzo6Jjp-IYUeYiin2efpMThMNPzAAcs1WXiIBddnXpHPx4eP_fOmeX162d83m8Dr3biBndS-874SIAxWuvaqqpytRYVSu05xp5X08woN1kgU3HIhwIGsOGqNnVyR2__cgIjtkOf2fGrPh8hfp0BV3A</recordid><startdate>200904</startdate><enddate>200904</enddate><creator>Geninatti, Sergio R.</creator><creator>Calvino, Manuel Hernandez</creator><creator>Benitez, Jose Ignacio Benavides</creator><creator>Mata, Nicolas Guil</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200904</creationdate><title>Concurrent calculations on reconfigurable logic devices applied to the analisys of video images</title><author>Geninatti, Sergio R. ; Calvino, Manuel Hernandez ; Benitez, Jose Ignacio Benavides ; Mata, Nicolas Guil</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-a538fbff62a29e687f466dc726e38db41d843f9908ac93e21c122ada361e88eb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Algorithm design and analysis</topic><topic>Circuits</topic><topic>Clocks</topic><topic>Concurrent computing</topic><topic>Field programmable gate arrays</topic><topic>Frequency</topic><topic>Hardware</topic><topic>Humans</topic><topic>Logic devices</topic><topic>Reconfigurable logic</topic><toplevel>online_resources</toplevel><creatorcontrib>Geninatti, Sergio R.</creatorcontrib><creatorcontrib>Calvino, Manuel Hernandez</creatorcontrib><creatorcontrib>Benitez, Jose Ignacio Benavides</creatorcontrib><creatorcontrib>Mata, Nicolas Guil</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Geninatti, Sergio R.</au><au>Calvino, Manuel Hernandez</au><au>Benitez, Jose Ignacio Benavides</au><au>Mata, Nicolas Guil</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Concurrent calculations on reconfigurable logic devices applied to the analisys of video images</atitle><btitle>2009 5th Southern Conference on Programmable Logic (SPL)</btitle><stitle>SPL</stitle><date>2009-04</date><risdate>2009</risdate><spage>109</spage><epage>114</epage><pages>109-114</pages><isbn>1424438470</isbn><isbn>9781424438471</isbn><abstract>This paper presents the design and implementation on FPGA devices of an algorithm for computing the similarity between neighbor photograms in a video sequence using luminance information. Making use of the well-known flexibility of reconfigurable logic devices, we have designed a hardware implementation of the algorithm used in video segmentation and indexation. The experimental work has established a tradeoff between concurrent sequential resources and functional blocks, in order to achieve maximum operation speed with minimum silicon area. In order to evaluate the efficiency of the designed system, we have compared the performance of the hardware solution with that of calculations done via software using general-purpose processors with and without the MMX extension.</abstract><pub>IEEE</pub><doi>10.1109/SPL.2009.4914889</doi><tpages>6</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Algorithm design and analysis Circuits Clocks Concurrent computing Field programmable gate arrays Frequency Hardware Humans Logic devices Reconfigurable logic |
title | Concurrent calculations on reconfigurable logic devices applied to the analisys of video images |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T04%3A21%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Concurrent%20calculations%20on%20reconfigurable%20logic%20devices%20applied%20to%20the%20analisys%20of%20video%20images&rft.btitle=2009%205th%20Southern%20Conference%20on%20Programmable%20Logic%20(SPL)&rft.au=Geninatti,%20Sergio%20R.&rft.date=2009-04&rft.spage=109&rft.epage=114&rft.pages=109-114&rft.isbn=1424438470&rft.isbn_list=9781424438471&rft_id=info:doi/10.1109/SPL.2009.4914889&rft_dat=%3Cieee_6IE%3E4914889%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4914889&rfr_iscdi=true |