Low power realization of FIR filters using multirate architectures
The paper presents low power realization of FIR filters using multirate architectures. The multirate architectures enable computationally efficient implementations of FIR filters. The computational complexity of these architectures is analysed and power analysis is presented to show how the computat...
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| creator | Mehendale, M. Sherlekar, S.D. Venkatesh, G. |
| description | The paper presents low power realization of FIR filters using multirate architectures. The multirate architectures enable computationally efficient implementations of FIR filters. The computational complexity of these architectures is analysed and power analysis is presented to show how the computational efficiency can be exploited to reduce power dissipation. The results show upto 73% power reduction for dedicated ASIC implementation with no datapath area overhead. The paper also presents the implementation of the multirate architecture on the TMS320C2x/C5x programmable DSPs and shows that it can result in upto 43% power reduction. |
| doi_str_mv | 10.1109/ICVD.1996.489637 |
| format | Conference Proceeding |
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The multirate architectures enable computationally efficient implementations of FIR filters. The computational complexity of these architectures is analysed and power analysis is presented to show how the computational efficiency can be exploited to reduce power dissipation. The results show upto 73% power reduction for dedicated ASIC implementation with no datapath area overhead. The paper also presents the implementation of the multirate architecture on the TMS320C2x/C5x programmable DSPs and shows that it can result in upto 43% power reduction.</description><identifier>ISSN: 1063-9667</identifier><identifier>ISBN: 0818672285</identifier><identifier>ISBN: 9780818672286</identifier><identifier>EISSN: 2380-6923</identifier><identifier>DOI: 10.1109/ICVD.1996.489637</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application specific integrated circuits ; Computational complexity ; Computer architecture ; Delay ; Digital signal processing ; Finite impulse response filter ; Instruments ; Pipeline processing ; Power dissipation ; Voltage</subject><ispartof>Proceedings of 9th International Conference on VLSI Design, 1996, p.370-375</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/489637$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2057,4049,4050,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/489637$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Mehendale, M.</creatorcontrib><creatorcontrib>Sherlekar, S.D.</creatorcontrib><creatorcontrib>Venkatesh, G.</creatorcontrib><title>Low power realization of FIR filters using multirate architectures</title><title>Proceedings of 9th International Conference on VLSI Design</title><addtitle>ICVD</addtitle><description>The paper presents low power realization of FIR filters using multirate architectures. The multirate architectures enable computationally efficient implementations of FIR filters. The computational complexity of these architectures is analysed and power analysis is presented to show how the computational efficiency can be exploited to reduce power dissipation. The results show upto 73% power reduction for dedicated ASIC implementation with no datapath area overhead. The paper also presents the implementation of the multirate architecture on the TMS320C2x/C5x programmable DSPs and shows that it can result in upto 43% power reduction.</description><subject>Application specific integrated circuits</subject><subject>Computational complexity</subject><subject>Computer architecture</subject><subject>Delay</subject><subject>Digital signal processing</subject><subject>Finite impulse response filter</subject><subject>Instruments</subject><subject>Pipeline processing</subject><subject>Power dissipation</subject><subject>Voltage</subject><issn>1063-9667</issn><issn>2380-6923</issn><isbn>0818672285</isbn><isbn>9780818672286</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotz01LwzAYwPHgC9hN7-IpX6DzyUuTPEetTgsFQdTrSJtEI9060pShn97DPP1vP_gTcs1gxRjgbVN_PKwYolpJg0roE1JwYaBUyMUpWYBhRmnOTXVGCgZKlKiUviCLafoGAFOBLsh9Ox7ofjz4RJO3Q_y1OY47Oga6bl5piEP2aaLzFHefdDsPOSabPbWp_4rZ93lOfrok58EOk7_675K8rx_f6ueyfXlq6ru2jAxkLpnFrtdCObQghWPAtHEGrONGKqc7FyqJTqNkoccOhdTBG-2RB-k60FYsyc3Rjd77zT7FrU0_m-O6-AOvb0uh</recordid><startdate>1996</startdate><enddate>1996</enddate><creator>Mehendale, M.</creator><creator>Sherlekar, S.D.</creator><creator>Venkatesh, G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1996</creationdate><title>Low power realization of FIR filters using multirate architectures</title><author>Mehendale, M. ; Sherlekar, S.D. ; Venkatesh, G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-1a9bc736d9a043d10178d80ad2846d7bdf549d7941fc9b9347fe87e92f4db07a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Application specific integrated circuits</topic><topic>Computational complexity</topic><topic>Computer architecture</topic><topic>Delay</topic><topic>Digital signal processing</topic><topic>Finite impulse response filter</topic><topic>Instruments</topic><topic>Pipeline processing</topic><topic>Power dissipation</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Mehendale, M.</creatorcontrib><creatorcontrib>Sherlekar, S.D.</creatorcontrib><creatorcontrib>Venkatesh, G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mehendale, M.</au><au>Sherlekar, S.D.</au><au>Venkatesh, G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low power realization of FIR filters using multirate architectures</atitle><btitle>Proceedings of 9th International Conference on VLSI Design</btitle><stitle>ICVD</stitle><date>1996</date><risdate>1996</risdate><spage>370</spage><epage>375</epage><pages>370-375</pages><issn>1063-9667</issn><eissn>2380-6923</eissn><isbn>0818672285</isbn><isbn>9780818672286</isbn><abstract>The paper presents low power realization of FIR filters using multirate architectures. The multirate architectures enable computationally efficient implementations of FIR filters. The computational complexity of these architectures is analysed and power analysis is presented to show how the computational efficiency can be exploited to reduce power dissipation. The results show upto 73% power reduction for dedicated ASIC implementation with no datapath area overhead. The paper also presents the implementation of the multirate architecture on the TMS320C2x/C5x programmable DSPs and shows that it can result in upto 43% power reduction.</abstract><pub>IEEE</pub><doi>10.1109/ICVD.1996.489637</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 1063-9667 |
| ispartof | Proceedings of 9th International Conference on VLSI Design, 1996, p.370-375 |
| issn | 1063-9667 2380-6923 |
| language | eng |
| recordid | cdi_ieee_primary_489637 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application specific integrated circuits Computational complexity Computer architecture Delay Digital signal processing Finite impulse response filter Instruments Pipeline processing Power dissipation Voltage |
| title | Low power realization of FIR filters using multirate architectures |
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