A 200 MHz 2.5 V 4 W superscalar RISC microprocessor

A 200 MHz 2.5 V 4 W superscalar RISC microprocessor

This RISC microprocessor is based on a microarchitecture designed in a 2.5 V CMOS technology. The 78.75 mm/sup 2/ design features dual 16 kB instruction and data caches, a floating-point unit, an integer unit, a branch unit, a load/store unit, and a system unit. Two instructions per cycle can be dis...

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Bibliographische Detailangaben
Hauptverfasser: Sanchez, H., Eisen, L., Croxton, C., Piejko, A., Nicoletta, C., Vo, I., Branson, B., Wen Wang, Quan Nguyen, Buti, T., Hsu, L., Saccamango, M.J., Ratanaphanyara, S., Philip, R., Alvarez, J., Weitzel, S., Gerosa, G.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitance
Clocks
CMOS technology
Energy consumption
Energy management
Logic arrays
Logic testing
Microprocessors
Phase locked loops
Reduced instruction set computing
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Beschreibung
Zusammenfassung:This RISC microprocessor is based on a microarchitecture designed in a 2.5 V CMOS technology. The 78.75 mm/sup 2/ design features dual 16 kB instruction and data caches, a floating-point unit, an integer unit, a branch unit, a load/store unit, and a system unit. Two instructions per cycle can be dispatched in this superscalar design. The user-configurable multiplying PLL provides a processor clock at 2/spl times/, 2.5/spl times/, 3/spl times/, 3.5/spl times/, 4/spl times/, 4.5/spl times/, 5/spl times/, 5.5/spl times/, and 6/spl times/ the bus clock frequency. Testability features include level-sensitive-scan-design (LSSD), array-built-in-self-test (ABIST) logic for cache and tag arrays, and a JTAG interface.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.1996.488578