Power supply noise reduction by clock scheduling with gate-level current waveform estimation
As technology progresses, power supply noise, such as IR-drop and L*di/dt drop, has become a major concern in power distribution network design. Since power supply noise is fundamentally caused by large current peaks, it can be minimized in early stages by deliberate clock scheduling which utilizes...
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creator | Yooseong Kim Sangwoo Han Juho Kim |
description | As technology progresses, power supply noise, such as IR-drop and L*di/dt drop, has become a major concern in power distribution network design. Since power supply noise is fundamentally caused by large current peaks, it can be minimized in early stages by deliberate clock scheduling which utilizes nonzero clock skew and does not violate timing constraints. In this paper, we propose a clock skew scheduling method to reduce power supply noise by minimizing the peak current. While previous approaches require extra characterization efforts to estimate supply current waveform of circuits, we approximate gate-level current waveform only with existing cell library information. Experimental results show that our method can reduce the peak current by 11.6% on average and the voltage variation in power lines by 18.3% on average. |
doi_str_mv | 10.1109/SOCDC.2008.4815710 |
format | Conference Proceeding |
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Since power supply noise is fundamentally caused by large current peaks, it can be minimized in early stages by deliberate clock scheduling which utilizes nonzero clock skew and does not violate timing constraints. In this paper, we propose a clock skew scheduling method to reduce power supply noise by minimizing the peak current. While previous approaches require extra characterization efforts to estimate supply current waveform of circuits, we approximate gate-level current waveform only with existing cell library information. Experimental results show that our method can reduce the peak current by 11.6% on average and the voltage variation in power lines by 18.3% on average.</description><identifier>ISBN: 1424425980</identifier><identifier>ISBN: 9781424425983</identifier><identifier>EISBN: 1424425999</identifier><identifier>EISBN: 9781424425990</identifier><identifier>DOI: 10.1109/SOCDC.2008.4815710</identifier><identifier>LCCN: 2008904863</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit noise ; clock scheduling ; Clocks ; current waveform estimation ; Libraries ; Logic ; Noise reduction ; peak current ; Power supplies ; power supply noise ; Scheduling ; simultaneous switching noise ; Timing ; Voltage ; Working environment noise</subject><ispartof>2008 International SoC Design Conference, 2008, Vol.2, p.II-166-II-169</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4815710$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4815710$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yooseong Kim</creatorcontrib><creatorcontrib>Sangwoo Han</creatorcontrib><creatorcontrib>Juho Kim</creatorcontrib><title>Power supply noise reduction by clock scheduling with gate-level current waveform estimation</title><title>2008 International SoC Design Conference</title><addtitle>SOCDC</addtitle><description>As technology progresses, power supply noise, such as IR-drop and L*di/dt drop, has become a major concern in power distribution network design. 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Experimental results show that our method can reduce the peak current by 11.6% on average and the voltage variation in power lines by 18.3% on average.</description><subject>Circuit noise</subject><subject>clock scheduling</subject><subject>Clocks</subject><subject>current waveform estimation</subject><subject>Libraries</subject><subject>Logic</subject><subject>Noise reduction</subject><subject>peak current</subject><subject>Power supplies</subject><subject>power supply noise</subject><subject>Scheduling</subject><subject>simultaneous switching noise</subject><subject>Timing</subject><subject>Voltage</subject><subject>Working environment noise</subject><isbn>1424425980</isbn><isbn>9781424425983</isbn><isbn>1424425999</isbn><isbn>9781424425990</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFUNFqwkAQvFKEVusPtC_3A7F72T0v91jS1hYEC_WxIPHc6LUxkbuo-PeNVOi-DLPszDArxL2CkVJgHz9n-XM-SgGyEWVKGwVXoq8oJUq1tfb6n2TQE_3zoQXKxngjhjF-QzekETXeiq-P5shBxv1uV51k3fjIMvBq71rf1HJ5kq5q3I-MbtMtK1-v5dG3G7kuWk4qPnAl3T4Erlt5LA5cNmErObZ-W5z1d6JXFlXk4QUHYv76Ms_fkuls8p4_TRNvoU0cpasxUsmFBmMICQww8MpgmZVolXZEjKlJOXMKx1YTOkZaGmtAqa7HQDz82XpmXuxClx5Oi8tn8BcfYFXs</recordid><startdate>200811</startdate><enddate>200811</enddate><creator>Yooseong Kim</creator><creator>Sangwoo Han</creator><creator>Juho Kim</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200811</creationdate><title>Power supply noise reduction by clock scheduling with gate-level current waveform estimation</title><author>Yooseong Kim ; Sangwoo Han ; Juho Kim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-c42d634fea5077434070e0ed73f8f3915c44e3272e8c1369543ce34b797011533</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Circuit noise</topic><topic>clock scheduling</topic><topic>Clocks</topic><topic>current waveform estimation</topic><topic>Libraries</topic><topic>Logic</topic><topic>Noise reduction</topic><topic>peak current</topic><topic>Power supplies</topic><topic>power supply noise</topic><topic>Scheduling</topic><topic>simultaneous switching noise</topic><topic>Timing</topic><topic>Voltage</topic><topic>Working environment noise</topic><toplevel>online_resources</toplevel><creatorcontrib>Yooseong Kim</creatorcontrib><creatorcontrib>Sangwoo Han</creatorcontrib><creatorcontrib>Juho Kim</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yooseong Kim</au><au>Sangwoo Han</au><au>Juho Kim</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Power supply noise reduction by clock scheduling with gate-level current waveform estimation</atitle><btitle>2008 International SoC Design Conference</btitle><stitle>SOCDC</stitle><date>2008-11</date><risdate>2008</risdate><volume>2</volume><spage>II-166</spage><epage>II-169</epage><pages>II-166-II-169</pages><isbn>1424425980</isbn><isbn>9781424425983</isbn><eisbn>1424425999</eisbn><eisbn>9781424425990</eisbn><abstract>As technology progresses, power supply noise, such as IR-drop and L*di/dt drop, has become a major concern in power distribution network design. Since power supply noise is fundamentally caused by large current peaks, it can be minimized in early stages by deliberate clock scheduling which utilizes nonzero clock skew and does not violate timing constraints. In this paper, we propose a clock skew scheduling method to reduce power supply noise by minimizing the peak current. While previous approaches require extra characterization efforts to estimate supply current waveform of circuits, we approximate gate-level current waveform only with existing cell library information. Experimental results show that our method can reduce the peak current by 11.6% on average and the voltage variation in power lines by 18.3% on average.</abstract><pub>IEEE</pub><doi>10.1109/SOCDC.2008.4815710</doi></addata></record> |
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subjects | Circuit noise clock scheduling Clocks current waveform estimation Libraries Logic Noise reduction peak current Power supplies power supply noise Scheduling simultaneous switching noise Timing Voltage Working environment noise |
title | Power supply noise reduction by clock scheduling with gate-level current waveform estimation |
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