Area-efficent power clamp circuit using gate-coupled structure for Smart Power ICs

Area-efficient ESD (Electro Static Discharge) power clamp using gate-coupled structure for Smart Power technology is proposed. The use of Big-FET parasitic Capacitance results in the reduction of the total size of the circuit when compared to the Darlington scheme and RC triggered circuits. The perf...

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Bibliographische Detailangaben
Hauptverfasser:	Dong-Jun Kim, Ju-Ho Park, Sang-Gyu Park
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clamps CMOS process CMOS technology Distributed parameter circuits Electrostatic discharge electrostatic discharge (ESD) gate-coupled structure Parasitic capacitance power clamp circui Power integrated circuits Power measurement Power transmission lines Pulse measurements smart power technology
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Beschreibung
Zusammenfassung:	Area-efficient ESD (Electro Static Discharge) power clamp using gate-coupled structure for Smart Power technology is proposed. The use of Big-FET parasitic Capacitance results in the reduction of the total size of the circuit when compared to the Darlington scheme and RC triggered circuits. The performance of the proposed ESD power clamp was successfully verified in a 0.35 um 60 V BCD (bipolar CMOS DMOS) process by TLP (Transmission Line Pulse) measurements.
DOI:	10.1109/SOCDC.2008.4815664