Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization
Back-end-of-line (BEOL) process variation is becoming more and more important since technology is scaling down and increases its complexity. On-chip capacitances and resistances are strongly dependent on the BEOL geometrical configuration so it is really important to have an accurate characterizatio...
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| creator | Bortesi, L. Vendrame, L. |
| description | Back-end-of-line (BEOL) process variation is becoming more and more important since technology is scaling down and increases its complexity. On-chip capacitances and resistances are strongly dependent on the BEOL geometrical configuration so it is really important to have an accurate characterization of the metal and dielectric thickness. Interconnect parasitic modelling by means of LPE tool (Layout Parasitic Extraction) or semi-analytic approximation can't neglect the impact of metal (dielectric) thickness variations. The focus of this work is to provide an accurate, simple and suitable for parametric testing methodology to electrically measure metal (dielectric) thickness, mandatory for a useful characterization and control of a technology. |
| doi_str_mv | 10.1109/ICMTS.2009.4814640 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4814640</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4814640</ieee_id><sourcerecordid>4814640</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-40a67dcc4e147b25b3a7368ab731dbe6b3ba9a2050ff3230d486e079af2892513</originalsourceid><addsrcrecordid>eNotkM1OwkAUhScqiYC8gG7mBYr3zkx_xp0WVBKIC3FNbttbO1JaMm1M8OmtkbM5m_N9iyPELcIcEez9Kt1s3-cKwM5NgiYycCHGCsMkQFD2UkzQKGOMCi1eiTFCjIEFrUZi8sdYUKD0tZh13RcMMaFGBWNRbLinWlJTyIXjmvPeu1xuK5fvG-66B0kybQ9HzxU3nftmOeyrtmjr9vMky9bLJ8r3wXLAl2d4sKUVecp79u6Hetc2N2JUUt3x7NxT8fG83KavwfrtZZU-rgOHcdgHBiiKizw3jCbOVJhpinWUUBZrLDKOMp2RJQUhlKVWGgqTRAyxpVIlVoWop-Lu3-uYeXf07kD-tDu_pX8B88taZg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Bortesi, L. ; Vendrame, L.</creator><creatorcontrib>Bortesi, L. ; Vendrame, L.</creatorcontrib><description>Back-end-of-line (BEOL) process variation is becoming more and more important since technology is scaling down and increases its complexity. On-chip capacitances and resistances are strongly dependent on the BEOL geometrical configuration so it is really important to have an accurate characterization of the metal and dielectric thickness. Interconnect parasitic modelling by means of LPE tool (Layout Parasitic Extraction) or semi-analytic approximation can't neglect the impact of metal (dielectric) thickness variations. The focus of this work is to provide an accurate, simple and suitable for parametric testing methodology to electrically measure metal (dielectric) thickness, mandatory for a useful characterization and control of a technology.</description><identifier>ISSN: 1071-9032</identifier><identifier>ISBN: 1424442591</identifier><identifier>ISBN: 9781424442591</identifier><identifier>EISSN: 2158-1029</identifier><identifier>DOI: 10.1109/ICMTS.2009.4814640</identifier><identifier>LCCN: 2009902023</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance measurement ; Dielectric measurements ; Electric variables measurement ; Fingers ; Integrated circuit interconnections ; Parasitic capacitance ; Research and development ; Space technology ; Thickness measurement ; US Department of Energy</subject><ispartof>2009 IEEE International Conference on Microelectronic Test Structures, 2009, p.196-200</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4814640$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4814640$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bortesi, L.</creatorcontrib><creatorcontrib>Vendrame, L.</creatorcontrib><title>Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization</title><title>2009 IEEE International Conference on Microelectronic Test Structures</title><addtitle>ICMTS</addtitle><description>Back-end-of-line (BEOL) process variation is becoming more and more important since technology is scaling down and increases its complexity. On-chip capacitances and resistances are strongly dependent on the BEOL geometrical configuration so it is really important to have an accurate characterization of the metal and dielectric thickness. Interconnect parasitic modelling by means of LPE tool (Layout Parasitic Extraction) or semi-analytic approximation can't neglect the impact of metal (dielectric) thickness variations. The focus of this work is to provide an accurate, simple and suitable for parametric testing methodology to electrically measure metal (dielectric) thickness, mandatory for a useful characterization and control of a technology.</description><subject>Capacitance measurement</subject><subject>Dielectric measurements</subject><subject>Electric variables measurement</subject><subject>Fingers</subject><subject>Integrated circuit interconnections</subject><subject>Parasitic capacitance</subject><subject>Research and development</subject><subject>Space technology</subject><subject>Thickness measurement</subject><subject>US Department of Energy</subject><issn>1071-9032</issn><issn>2158-1029</issn><isbn>1424442591</isbn><isbn>9781424442591</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkM1OwkAUhScqiYC8gG7mBYr3zkx_xp0WVBKIC3FNbttbO1JaMm1M8OmtkbM5m_N9iyPELcIcEez9Kt1s3-cKwM5NgiYycCHGCsMkQFD2UkzQKGOMCi1eiTFCjIEFrUZi8sdYUKD0tZh13RcMMaFGBWNRbLinWlJTyIXjmvPeu1xuK5fvG-66B0kybQ9HzxU3nftmOeyrtmjr9vMky9bLJ8r3wXLAl2d4sKUVecp79u6Hetc2N2JUUt3x7NxT8fG83KavwfrtZZU-rgOHcdgHBiiKizw3jCbOVJhpinWUUBZrLDKOMp2RJQUhlKVWGgqTRAyxpVIlVoWop-Lu3-uYeXf07kD-tDu_pX8B88taZg</recordid><startdate>200903</startdate><enddate>200903</enddate><creator>Bortesi, L.</creator><creator>Vendrame, L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200903</creationdate><title>Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization</title><author>Bortesi, L. ; Vendrame, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-40a67dcc4e147b25b3a7368ab731dbe6b3ba9a2050ff3230d486e079af2892513</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Capacitance measurement</topic><topic>Dielectric measurements</topic><topic>Electric variables measurement</topic><topic>Fingers</topic><topic>Integrated circuit interconnections</topic><topic>Parasitic capacitance</topic><topic>Research and development</topic><topic>Space technology</topic><topic>Thickness measurement</topic><topic>US Department of Energy</topic><toplevel>online_resources</toplevel><creatorcontrib>Bortesi, L.</creatorcontrib><creatorcontrib>Vendrame, L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bortesi, L.</au><au>Vendrame, L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization</atitle><btitle>2009 IEEE International Conference on Microelectronic Test Structures</btitle><stitle>ICMTS</stitle><date>2009-03</date><risdate>2009</risdate><spage>196</spage><epage>200</epage><pages>196-200</pages><issn>1071-9032</issn><eissn>2158-1029</eissn><isbn>1424442591</isbn><isbn>9781424442591</isbn><abstract>Back-end-of-line (BEOL) process variation is becoming more and more important since technology is scaling down and increases its complexity. On-chip capacitances and resistances are strongly dependent on the BEOL geometrical configuration so it is really important to have an accurate characterization of the metal and dielectric thickness. Interconnect parasitic modelling by means of LPE tool (Layout Parasitic Extraction) or semi-analytic approximation can't neglect the impact of metal (dielectric) thickness variations. The focus of this work is to provide an accurate, simple and suitable for parametric testing methodology to electrically measure metal (dielectric) thickness, mandatory for a useful characterization and control of a technology.</abstract><pub>IEEE</pub><doi>10.1109/ICMTS.2009.4814640</doi><tpages>5</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitance measurement Dielectric measurements Electric variables measurement Fingers Integrated circuit interconnections Parasitic capacitance Research and development Space technology Thickness measurement US Department of Energy |
| title | Metal and Dielectric Thickness: a Comprehensive Methodology for Back-End Electrical Characterization |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-21T18%3A40%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Metal%20and%20Dielectric%20Thickness:%20a%20Comprehensive%20Methodology%20for%20Back-End%20Electrical%20Characterization&rft.btitle=2009%20IEEE%20International%20Conference%20on%20Microelectronic%20Test%20Structures&rft.au=Bortesi,%20L.&rft.date=2009-03&rft.spage=196&rft.epage=200&rft.pages=196-200&rft.issn=1071-9032&rft.eissn=2158-1029&rft.isbn=1424442591&rft.isbn_list=9781424442591&rft_id=info:doi/10.1109/ICMTS.2009.4814640&rft_dat=%3Cieee_6IE%3E4814640%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4814640&rfr_iscdi=true |