A case study on logic diagnosis for System-on-Chip
This paper presents an industrial case study on logic diagnosis targeting system-on-chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the effect-cause paradigm. This approach consists of two phases: (i) a fault loca...
Gespeichert in:
| Hauptverfasser: | , , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 259 |
|---|---|
| container_issue | |
| container_start_page | 253 |
| container_title | |
| container_volume | |
| creator | Benabboud, Y. Bosio, A. Girard, P. Pravossoudovitch, S. Virazel, A. Bouzaida, L. Izaute, I. |
| description | This paper presents an industrial case study on logic diagnosis targeting system-on-chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the effect-cause paradigm. This approach consists of two phases: (i) a fault localization phase resorting to the critical path tracing to determine a set of suspects, (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. To deal with SoC we define a new algebra for the critical path tracing process during fault localization. Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach. |
| doi_str_mv | 10.1109/ISQED.2009.4810303 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>hal_6IE</sourceid><recordid>TN_cdi_ieee_primary_4810303</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4810303</ieee_id><sourcerecordid>oai_HAL_lirmm_00370646v1</sourcerecordid><originalsourceid>FETCH-LOGICAL-h211t-abbf45421673e37d57b08b545619e2d6d36b349cbcd1a87d1149a26b23655e1d3</originalsourceid><addsrcrecordid>eNpFkF1LAkEYhacPIbX-QN3Mfay973zPpZilIERY18vMzqgTu27sWOC_T1Ds6nA4D8_FIeQeYYQI9mm-fJ8-jxiAHQmDwIFfkAEKJgSzkqtL0kcrTMEP7ep_YOb6PBjdI4ODwFgwmrMbMsj5C0BIqU2fsDGtXI40737CnrZbWrfrVNGQ3Hrb5pTpqu3ocp93sSnabTHZpO9b0lu5Ose7Uw7J58v0YzIrFm-v88l4UWwY4q5w3q-EFAyV5pHrILUH46WQCm1kQQWuPBe28lVAZ3RAFNYx5RlXUkYMfEgej96Nq8vvLjWu25etS-VsvCjr1DVNCcA1KKF-8UA_HOkUYzzjp8_4H4C8V1I</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A case study on logic diagnosis for System-on-Chip</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Benabboud, Y. ; Bosio, A. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Bouzaida, L. ; Izaute, I.</creator><creatorcontrib>Benabboud, Y. ; Bosio, A. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Bouzaida, L. ; Izaute, I.</creatorcontrib><description>This paper presents an industrial case study on logic diagnosis targeting system-on-chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the effect-cause paradigm. This approach consists of two phases: (i) a fault localization phase resorting to the critical path tracing to determine a set of suspects, (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. To deal with SoC we define a new algebra for the critical path tracing process during fault localization. Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.</description><identifier>ISSN: 1948-3287</identifier><identifier>ISBN: 1424429528</identifier><identifier>ISBN: 9781424429523</identifier><identifier>ISBN: 1424429536</identifier><identifier>ISBN: 9781424429530</identifier><identifier>EISSN: 1948-3295</identifier><identifier>EISBN: 1424429536</identifier><identifier>EISBN: 9781424429530</identifier><identifier>DOI: 10.1109/ISQED.2009.4810303</identifier><identifier>LCCN: 2008908732</identifier><language>eng</language><publisher>IEEE</publisher><subject>Algebra ; Circuit faults ; Circuit simulation ; Electronics industry ; Engineering Sciences ; Fault diagnosis ; Fault Model ; Logic Diagnosis ; Logic functions ; Logic gates ; Micro and nanotechnologies ; Microelectronics ; Service robots ; SoC ; System-on-a-chip ; Testing</subject><ispartof>2009 10th International Symposium on Quality Electronic Design, 2009, p.253-259</ispartof><rights>Distributed under a Creative Commons Attribution 4.0 International License</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>0000-0003-0722-8772 ; 0000-0001-7398-7107 ; 0000-0001-6116-7339</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4810303$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,881,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4810303$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttps://hal-lirmm.ccsd.cnrs.fr/lirmm-00370646$$DView record in HAL$$Hfree_for_read</backlink></links><search><creatorcontrib>Benabboud, Y.</creatorcontrib><creatorcontrib>Bosio, A.</creatorcontrib><creatorcontrib>Girard, P.</creatorcontrib><creatorcontrib>Pravossoudovitch, S.</creatorcontrib><creatorcontrib>Virazel, A.</creatorcontrib><creatorcontrib>Bouzaida, L.</creatorcontrib><creatorcontrib>Izaute, I.</creatorcontrib><title>A case study on logic diagnosis for System-on-Chip</title><title>2009 10th International Symposium on Quality Electronic Design</title><addtitle>ISQED</addtitle><description>This paper presents an industrial case study on logic diagnosis targeting system-on-chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the effect-cause paradigm. This approach consists of two phases: (i) a fault localization phase resorting to the critical path tracing to determine a set of suspects, (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. To deal with SoC we define a new algebra for the critical path tracing process during fault localization. Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.</description><subject>Algebra</subject><subject>Circuit faults</subject><subject>Circuit simulation</subject><subject>Electronics industry</subject><subject>Engineering Sciences</subject><subject>Fault diagnosis</subject><subject>Fault Model</subject><subject>Logic Diagnosis</subject><subject>Logic functions</subject><subject>Logic gates</subject><subject>Micro and nanotechnologies</subject><subject>Microelectronics</subject><subject>Service robots</subject><subject>SoC</subject><subject>System-on-a-chip</subject><subject>Testing</subject><issn>1948-3287</issn><issn>1948-3295</issn><isbn>1424429528</isbn><isbn>9781424429523</isbn><isbn>1424429536</isbn><isbn>9781424429530</isbn><isbn>1424429536</isbn><isbn>9781424429530</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkF1LAkEYhacPIbX-QN3Mfay973zPpZilIERY18vMzqgTu27sWOC_T1Ds6nA4D8_FIeQeYYQI9mm-fJ8-jxiAHQmDwIFfkAEKJgSzkqtL0kcrTMEP7ep_YOb6PBjdI4ODwFgwmrMbMsj5C0BIqU2fsDGtXI40737CnrZbWrfrVNGQ3Hrb5pTpqu3ocp93sSnabTHZpO9b0lu5Ose7Uw7J58v0YzIrFm-v88l4UWwY4q5w3q-EFAyV5pHrILUH46WQCm1kQQWuPBe28lVAZ3RAFNYx5RlXUkYMfEgej96Nq8vvLjWu25etS-VsvCjr1DVNCcA1KKF-8UA_HOkUYzzjp8_4H4C8V1I</recordid><startdate>200903</startdate><enddate>200903</enddate><creator>Benabboud, Y.</creator><creator>Bosio, A.</creator><creator>Girard, P.</creator><creator>Pravossoudovitch, S.</creator><creator>Virazel, A.</creator><creator>Bouzaida, L.</creator><creator>Izaute, I.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>1XC</scope><orcidid>https://orcid.org/0000-0003-0722-8772</orcidid><orcidid>https://orcid.org/0000-0001-7398-7107</orcidid><orcidid>https://orcid.org/0000-0001-6116-7339</orcidid></search><sort><creationdate>200903</creationdate><title>A case study on logic diagnosis for System-on-Chip</title><author>Benabboud, Y. ; Bosio, A. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Bouzaida, L. ; Izaute, I.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-h211t-abbf45421673e37d57b08b545619e2d6d36b349cbcd1a87d1149a26b23655e1d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Algebra</topic><topic>Circuit faults</topic><topic>Circuit simulation</topic><topic>Electronics industry</topic><topic>Engineering Sciences</topic><topic>Fault diagnosis</topic><topic>Fault Model</topic><topic>Logic Diagnosis</topic><topic>Logic functions</topic><topic>Logic gates</topic><topic>Micro and nanotechnologies</topic><topic>Microelectronics</topic><topic>Service robots</topic><topic>SoC</topic><topic>System-on-a-chip</topic><topic>Testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Benabboud, Y.</creatorcontrib><creatorcontrib>Bosio, A.</creatorcontrib><creatorcontrib>Girard, P.</creatorcontrib><creatorcontrib>Pravossoudovitch, S.</creatorcontrib><creatorcontrib>Virazel, A.</creatorcontrib><creatorcontrib>Bouzaida, L.</creatorcontrib><creatorcontrib>Izaute, I.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Hyper Article en Ligne (HAL)</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Benabboud, Y.</au><au>Bosio, A.</au><au>Girard, P.</au><au>Pravossoudovitch, S.</au><au>Virazel, A.</au><au>Bouzaida, L.</au><au>Izaute, I.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A case study on logic diagnosis for System-on-Chip</atitle><btitle>2009 10th International Symposium on Quality Electronic Design</btitle><stitle>ISQED</stitle><date>2009-03</date><risdate>2009</risdate><spage>253</spage><epage>259</epage><pages>253-259</pages><issn>1948-3287</issn><eissn>1948-3295</eissn><isbn>1424429528</isbn><isbn>9781424429523</isbn><isbn>1424429536</isbn><isbn>9781424429530</isbn><eisbn>1424429536</eisbn><eisbn>9781424429530</eisbn><abstract>This paper presents an industrial case study on logic diagnosis targeting system-on-chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the effect-cause paradigm. This approach consists of two phases: (i) a fault localization phase resorting to the critical path tracing to determine a set of suspects, (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. To deal with SoC we define a new algebra for the critical path tracing process during fault localization. Experimental results show the diagnosis accuracy, in terms of absolute number of suspects, of the proposed approach. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.</abstract><pub>IEEE</pub><doi>10.1109/ISQED.2009.4810303</doi><tpages>7</tpages><orcidid>https://orcid.org/0000-0003-0722-8772</orcidid><orcidid>https://orcid.org/0000-0001-7398-7107</orcidid><orcidid>https://orcid.org/0000-0001-6116-7339</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1948-3287 |
| ispartof | 2009 10th International Symposium on Quality Electronic Design, 2009, p.253-259 |
| issn | 1948-3287 1948-3295 |
| language | eng |
| recordid | cdi_ieee_primary_4810303 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algebra Circuit faults Circuit simulation Electronics industry Engineering Sciences Fault diagnosis Fault Model Logic Diagnosis Logic functions Logic gates Micro and nanotechnologies Microelectronics Service robots SoC System-on-a-chip Testing |
| title | A case study on logic diagnosis for System-on-Chip |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T23%3A53%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-hal_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20case%20study%20on%20logic%20diagnosis%20for%20System-on-Chip&rft.btitle=2009%2010th%20International%20Symposium%20on%20Quality%20Electronic%20Design&rft.au=Benabboud,%20Y.&rft.date=2009-03&rft.spage=253&rft.epage=259&rft.pages=253-259&rft.issn=1948-3287&rft.eissn=1948-3295&rft.isbn=1424429528&rft.isbn_list=9781424429523&rft.isbn_list=1424429536&rft.isbn_list=9781424429530&rft_id=info:doi/10.1109/ISQED.2009.4810303&rft_dat=%3Chal_6IE%3Eoai_HAL_lirmm_00370646v1%3C/hal_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424429536&rft.eisbn_list=9781424429530&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4810303&rfr_iscdi=true |