Yield evaluation of analog placement with arbitrary capacitor ratio
Capacitance mismatch can be generally attributed two sources of errors: random mismatch and systematic mismatch. Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the syste...
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creator | Jwu-E Chen Pei-Wen Luo Chin-Long Wey |
description | Capacitance mismatch can be generally attributed two sources of errors: random mismatch and systematic mismatch. Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the systematic mismatch, but not the random mismatch. Based on spatial correlation model, this study derives the relationship among correlation, mismatch, and variation of capacitance ratio. Results show that the placement of unit capacitance array with higher correlation results in lower mismatch and lower variation of capacitance ratio. For any arbitrary capacitance ratio, i.e., more than two capacitors, if the summation of correlation coefficients for all capacitance pairs is defined as "index", the placement with higher index results in higher yield, where the yield is defined as the ratio of the acceptable designs over the sample size. In other words, one can find a near-optimal placement which has better yield by using the simple calculation of index, instead of the complicated circuit simulations. |
doi_str_mv | 10.1109/ISQED.2009.4810290 |
format | Conference Proceeding |
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Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the systematic mismatch, but not the random mismatch. Based on spatial correlation model, this study derives the relationship among correlation, mismatch, and variation of capacitance ratio. Results show that the placement of unit capacitance array with higher correlation results in lower mismatch and lower variation of capacitance ratio. For any arbitrary capacitance ratio, i.e., more than two capacitors, if the summation of correlation coefficients for all capacitance pairs is defined as "index", the placement with higher index results in higher yield, where the yield is defined as the ratio of the acceptable designs over the sample size. In other words, one can find a near-optimal placement which has better yield by using the simple calculation of index, instead of the complicated circuit simulations.</description><identifier>ISSN: 1948-3287</identifier><identifier>ISBN: 1424429528</identifier><identifier>ISBN: 9781424429523</identifier><identifier>EISSN: 1948-3295</identifier><identifier>EISBN: 1424429536</identifier><identifier>EISBN: 9781424429530</identifier><identifier>DOI: 10.1109/ISQED.2009.4810290</identifier><identifier>LCCN: 2008908732</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; capacitance mismatch ; Capacitors ; Circuit simulation ; CMOS technology ; Numerical analysis ; process variation ; Reactive power ; Routing ; Spatial correlation ; yield analysis ; Yield Evaluation</subject><ispartof>2009 10th International Symposium on Quality Electronic Design, 2009, p.179-184</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4810290$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27923,54918</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4810290$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jwu-E Chen</creatorcontrib><creatorcontrib>Pei-Wen Luo</creatorcontrib><creatorcontrib>Chin-Long Wey</creatorcontrib><title>Yield evaluation of analog placement with arbitrary capacitor ratio</title><title>2009 10th International Symposium on Quality Electronic Design</title><addtitle>ISQED</addtitle><description>Capacitance mismatch can be generally attributed two sources of errors: random mismatch and systematic mismatch. Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the systematic mismatch, but not the random mismatch. Based on spatial correlation model, this study derives the relationship among correlation, mismatch, and variation of capacitance ratio. Results show that the placement of unit capacitance array with higher correlation results in lower mismatch and lower variation of capacitance ratio. For any arbitrary capacitance ratio, i.e., more than two capacitors, if the summation of correlation coefficients for all capacitance pairs is defined as "index", the placement with higher index results in higher yield, where the yield is defined as the ratio of the acceptable designs over the sample size. In other words, one can find a near-optimal placement which has better yield by using the simple calculation of index, instead of the complicated circuit simulations.</description><subject>Capacitance</subject><subject>capacitance mismatch</subject><subject>Capacitors</subject><subject>Circuit simulation</subject><subject>CMOS technology</subject><subject>Numerical analysis</subject><subject>process variation</subject><subject>Reactive power</subject><subject>Routing</subject><subject>Spatial correlation</subject><subject>yield analysis</subject><subject>Yield Evaluation</subject><issn>1948-3287</issn><issn>1948-3295</issn><isbn>1424429528</isbn><isbn>9781424429523</isbn><isbn>1424429536</isbn><isbn>9781424429530</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkNtKxDAYhONhwe3qC-hNXqD1z6lJLqWuurAgol54tfyNqUa6bUmj4ttbcdGrYRhm-BhCThkUjIE9X93fLS8LDmALaRhwC3skY5JLya0S5T6ZMytNLiZ38B9wc_gXGD0j2TRgLBgt-BHJxvENQCqlzZxUT8G3z9R_YPuOKfQd7RuKHbb9Cx1adH7ru0Q_Q3qlGOuQIsYv6nBAF1IfafzpHJNZg-3oT3a6II9Xy4fqJl_fXq-qi3UemFYplxqERVHW2jjNHZTAFCrRKOt1w_QEZyb2kqOofS2VkKCt1c6UyjZSCysW5Ox3N3jvN0MM2wlms7tFfANml08K</recordid><startdate>200903</startdate><enddate>200903</enddate><creator>Jwu-E Chen</creator><creator>Pei-Wen Luo</creator><creator>Chin-Long Wey</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200903</creationdate><title>Yield evaluation of analog placement with arbitrary capacitor ratio</title><author>Jwu-E Chen ; Pei-Wen Luo ; Chin-Long Wey</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-47039a36b78c72c06015a53f59e7f17873842962a3beb453407997c8659f47393</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Capacitance</topic><topic>capacitance mismatch</topic><topic>Capacitors</topic><topic>Circuit simulation</topic><topic>CMOS technology</topic><topic>Numerical analysis</topic><topic>process variation</topic><topic>Reactive power</topic><topic>Routing</topic><topic>Spatial correlation</topic><topic>yield analysis</topic><topic>Yield Evaluation</topic><toplevel>online_resources</toplevel><creatorcontrib>Jwu-E Chen</creatorcontrib><creatorcontrib>Pei-Wen Luo</creatorcontrib><creatorcontrib>Chin-Long Wey</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jwu-E Chen</au><au>Pei-Wen Luo</au><au>Chin-Long Wey</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Yield evaluation of analog placement with arbitrary capacitor ratio</atitle><btitle>2009 10th International Symposium on Quality Electronic Design</btitle><stitle>ISQED</stitle><date>2009-03</date><risdate>2009</risdate><spage>179</spage><epage>184</epage><pages>179-184</pages><issn>1948-3287</issn><eissn>1948-3295</eissn><isbn>1424429528</isbn><isbn>9781424429523</isbn><eisbn>1424429536</eisbn><eisbn>9781424429530</eisbn><abstract>Capacitance mismatch can be generally attributed two sources of errors: random mismatch and systematic mismatch. Random mismatch is caused by the process variation, while systematic mismatch is mainly due to asymmetrical layout and processing gradients. Common centroid structure may reduce the systematic mismatch, but not the random mismatch. Based on spatial correlation model, this study derives the relationship among correlation, mismatch, and variation of capacitance ratio. Results show that the placement of unit capacitance array with higher correlation results in lower mismatch and lower variation of capacitance ratio. For any arbitrary capacitance ratio, i.e., more than two capacitors, if the summation of correlation coefficients for all capacitance pairs is defined as "index", the placement with higher index results in higher yield, where the yield is defined as the ratio of the acceptable designs over the sample size. In other words, one can find a near-optimal placement which has better yield by using the simple calculation of index, instead of the complicated circuit simulations.</abstract><pub>IEEE</pub><doi>10.1109/ISQED.2009.4810290</doi><tpages>6</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Capacitance capacitance mismatch Capacitors Circuit simulation CMOS technology Numerical analysis process variation Reactive power Routing Spatial correlation yield analysis Yield Evaluation |
title | Yield evaluation of analog placement with arbitrary capacitor ratio |
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