First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling
V t -mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to r...
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| creator | Merelle, T. Curatola, G. Nackaerts, A. Collaert, N. van Dal, M.J.H. Doornbos, G. Doorn, T.S. Christie, P. Vellianitis, G. Duriez, B. Duffy, R. Pawlak, B.J. Voogt, F.C. Rooyackers, R. Witters, L. Jurczak, M. Lander, R.J.P. |
| description | V t -mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in beta-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology. |
| doi_str_mv | 10.1109/IEDM.2008.4796662 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4796662</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4796662</ieee_id><sourcerecordid>4796662</sourcerecordid><originalsourceid>FETCH-LOGICAL-i156t-e856cf75f699cb4248380298e1ff02d77c6f8faf1ffa1194a02f17d61b0c08f13</originalsourceid><addsrcrecordid>eNpVkMtqwzAQRdUXNE3zAaUb_YBdjWzrsQxp0gYSCn1Ad0GWpWRK_MByA-3XV5Bsupo79zCXyxByBywFYPphOX9cp5wxleZSCyH4GZloqSDnec6zKM7JiEMhEgby8-Ifk_klGTEQWQIa1DW5CeGLMS4LXYyIXWAfBtqWwfUHM2Db0NbTBTaL-TsNnbPo0dIaQ20Gu6Ol25kDtj01TUXbbsAaf49X22-s3B4bF6iP_O11uqbBmuhsb8mVN_vgJqc5Jh8xffacrF6elrPpKsFYfEicKoT1svBCa1vG8ipTjGvlwHvGKymt8MobH1cDoHPDuAdZCSiZZcpDNib3x1x0zm26HmvT_2xO_8r-AJMFWzg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Merelle, T. ; Curatola, G. ; Nackaerts, A. ; Collaert, N. ; van Dal, M.J.H. ; Doornbos, G. ; Doorn, T.S. ; Christie, P. ; Vellianitis, G. ; Duriez, B. ; Duffy, R. ; Pawlak, B.J. ; Voogt, F.C. ; Rooyackers, R. ; Witters, L. ; Jurczak, M. ; Lander, R.J.P.</creator><creatorcontrib>Merelle, T. ; Curatola, G. ; Nackaerts, A. ; Collaert, N. ; van Dal, M.J.H. ; Doornbos, G. ; Doorn, T.S. ; Christie, P. ; Vellianitis, G. ; Duriez, B. ; Duffy, R. ; Pawlak, B.J. ; Voogt, F.C. ; Rooyackers, R. ; Witters, L. ; Jurczak, M. ; Lander, R.J.P.</creatorcontrib><description>V t -mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in beta-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.</description><identifier>ISSN: 0163-1918</identifier><identifier>ISBN: 9781424423774</identifier><identifier>ISBN: 1424423775</identifier><identifier>EISSN: 2156-017X</identifier><identifier>EISBN: 9781424423781</identifier><identifier>EISBN: 1424423783</identifier><identifier>DOI: 10.1109/IEDM.2008.4796662</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>CMOS technology ; Design optimization ; Doping ; FinFETs ; Fluctuations ; Guidelines ; MOS devices ; Random access memory ; Scalability ; Transistors</subject><ispartof>2008 IEEE International Electron Devices Meeting, 2008, p.1-4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4796662$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4796662$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Merelle, T.</creatorcontrib><creatorcontrib>Curatola, G.</creatorcontrib><creatorcontrib>Nackaerts, A.</creatorcontrib><creatorcontrib>Collaert, N.</creatorcontrib><creatorcontrib>van Dal, M.J.H.</creatorcontrib><creatorcontrib>Doornbos, G.</creatorcontrib><creatorcontrib>Doorn, T.S.</creatorcontrib><creatorcontrib>Christie, P.</creatorcontrib><creatorcontrib>Vellianitis, G.</creatorcontrib><creatorcontrib>Duriez, B.</creatorcontrib><creatorcontrib>Duffy, R.</creatorcontrib><creatorcontrib>Pawlak, B.J.</creatorcontrib><creatorcontrib>Voogt, F.C.</creatorcontrib><creatorcontrib>Rooyackers, R.</creatorcontrib><creatorcontrib>Witters, L.</creatorcontrib><creatorcontrib>Jurczak, M.</creatorcontrib><creatorcontrib>Lander, R.J.P.</creatorcontrib><title>First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling</title><title>2008 IEEE International Electron Devices Meeting</title><addtitle>IEDM</addtitle><description>V t -mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in beta-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.</description><subject>CMOS technology</subject><subject>Design optimization</subject><subject>Doping</subject><subject>FinFETs</subject><subject>Fluctuations</subject><subject>Guidelines</subject><subject>MOS devices</subject><subject>Random access memory</subject><subject>Scalability</subject><subject>Transistors</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>9781424423774</isbn><isbn>1424423775</isbn><isbn>9781424423781</isbn><isbn>1424423783</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtqwzAQRdUXNE3zAaUb_YBdjWzrsQxp0gYSCn1Ad0GWpWRK_MByA-3XV5Bsupo79zCXyxByBywFYPphOX9cp5wxleZSCyH4GZloqSDnec6zKM7JiEMhEgby8-Ifk_klGTEQWQIa1DW5CeGLMS4LXYyIXWAfBtqWwfUHM2Db0NbTBTaL-TsNnbPo0dIaQ20Gu6Ol25kDtj01TUXbbsAaf49X22-s3B4bF6iP_O11uqbBmuhsb8mVN_vgJqc5Jh8xffacrF6elrPpKsFYfEicKoT1svBCa1vG8ipTjGvlwHvGKymt8MobH1cDoHPDuAdZCSiZZcpDNib3x1x0zm26HmvT_2xO_8r-AJMFWzg</recordid><startdate>200812</startdate><enddate>200812</enddate><creator>Merelle, T.</creator><creator>Curatola, G.</creator><creator>Nackaerts, A.</creator><creator>Collaert, N.</creator><creator>van Dal, M.J.H.</creator><creator>Doornbos, G.</creator><creator>Doorn, T.S.</creator><creator>Christie, P.</creator><creator>Vellianitis, G.</creator><creator>Duriez, B.</creator><creator>Duffy, R.</creator><creator>Pawlak, B.J.</creator><creator>Voogt, F.C.</creator><creator>Rooyackers, R.</creator><creator>Witters, L.</creator><creator>Jurczak, M.</creator><creator>Lander, R.J.P.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200812</creationdate><title>First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling</title><author>Merelle, T. ; Curatola, G. ; Nackaerts, A. ; Collaert, N. ; van Dal, M.J.H. ; Doornbos, G. ; Doorn, T.S. ; Christie, P. ; Vellianitis, G. ; Duriez, B. ; Duffy, R. ; Pawlak, B.J. ; Voogt, F.C. ; Rooyackers, R. ; Witters, L. ; Jurczak, M. ; Lander, R.J.P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i156t-e856cf75f699cb4248380298e1ff02d77c6f8faf1ffa1194a02f17d61b0c08f13</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2008</creationdate><topic>CMOS technology</topic><topic>Design optimization</topic><topic>Doping</topic><topic>FinFETs</topic><topic>Fluctuations</topic><topic>Guidelines</topic><topic>MOS devices</topic><topic>Random access memory</topic><topic>Scalability</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Merelle, T.</creatorcontrib><creatorcontrib>Curatola, G.</creatorcontrib><creatorcontrib>Nackaerts, A.</creatorcontrib><creatorcontrib>Collaert, N.</creatorcontrib><creatorcontrib>van Dal, M.J.H.</creatorcontrib><creatorcontrib>Doornbos, G.</creatorcontrib><creatorcontrib>Doorn, T.S.</creatorcontrib><creatorcontrib>Christie, P.</creatorcontrib><creatorcontrib>Vellianitis, G.</creatorcontrib><creatorcontrib>Duriez, B.</creatorcontrib><creatorcontrib>Duffy, R.</creatorcontrib><creatorcontrib>Pawlak, B.J.</creatorcontrib><creatorcontrib>Voogt, F.C.</creatorcontrib><creatorcontrib>Rooyackers, R.</creatorcontrib><creatorcontrib>Witters, L.</creatorcontrib><creatorcontrib>Jurczak, M.</creatorcontrib><creatorcontrib>Lander, R.J.P.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Merelle, T.</au><au>Curatola, G.</au><au>Nackaerts, A.</au><au>Collaert, N.</au><au>van Dal, M.J.H.</au><au>Doornbos, G.</au><au>Doorn, T.S.</au><au>Christie, P.</au><au>Vellianitis, G.</au><au>Duriez, B.</au><au>Duffy, R.</au><au>Pawlak, B.J.</au><au>Voogt, F.C.</au><au>Rooyackers, R.</au><au>Witters, L.</au><au>Jurczak, M.</au><au>Lander, R.J.P.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling</atitle><btitle>2008 IEEE International Electron Devices Meeting</btitle><stitle>IEDM</stitle><date>2008-12</date><risdate>2008</risdate><spage>1</spage><epage>4</epage><pages>1-4</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><isbn>9781424423774</isbn><isbn>1424423775</isbn><eisbn>9781424423781</eisbn><eisbn>1424423783</eisbn><abstract>V t -mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in beta-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.</abstract><pub>IEEE</pub><doi>10.1109/IEDM.2008.4796662</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 0163-1918 |
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| language | eng ; jpn |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS technology Design optimization Doping FinFETs Fluctuations Guidelines MOS devices Random access memory Scalability Transistors |
| title | First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T10%3A03%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=First%20observation%20of%20FinFET%20specific%20mismatch%20behavior%20and%20optimization%20guidelines%20for%20SRAM%20scaling&rft.btitle=2008%20IEEE%20International%20Electron%20Devices%20Meeting&rft.au=Merelle,%20T.&rft.date=2008-12&rft.spage=1&rft.epage=4&rft.pages=1-4&rft.issn=0163-1918&rft.eissn=2156-017X&rft.isbn=9781424423774&rft.isbn_list=1424423775&rft_id=info:doi/10.1109/IEDM.2008.4796662&rft_dat=%3Cieee_6IE%3E4796662%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424423781&rft.eisbn_list=1424423783&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4796662&rfr_iscdi=true |