A criticality-driven microarchitectural three dimensional (3D) floorplanner

As technology scales, interconnect delays begin to dominate the performance of modern microprocessors. The ability to reduce the length of global wires has become an important design constraint, however only a subset of those global wires is critical for determining performance. The introduction of...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Sridharan, S., DeBole, M., Guangyu Sun, Yuan Xie, Narayanan, V.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Cost function Delay Feedback loop Microarchitecture Microprocessors Pipelines Stacking Sun Wire Wiring
Online-Zugang:	Volltext bestellen
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